Clash can't represent 300 MHz exactly

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

https://clash-lang.org/

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Clash can't represent 300 MHz exactly #2811

Open martijnbastiaan opened 5 days ago

martijnbastiaan commented 5 days ago

See: https://github.com/bittide/bittide-hardware/pull/643

I don't think Bittide's case makes a particular strong case for changing anything. "Normal" projects don't care about a couple of PPMs clock differences. This might however prohibit writing multicycle path constraints.

martijnbastiaan commented 5 days ago

Slack discussion (can't figure out how to properly copy stuff..):

Screenshot from 2024-09-24 15-41-43