Help with design low-level HDL language

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

https://clash-lang.org/

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Help with design low-level HDL language #417

Open XVilka opened 5 years ago

XVilka commented 5 years ago

FPGA world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help everyone, so HDL implementations will opt only for generating this low-level HDL and routing/synthesizers accept it. LLVM or WebAssembly - you can see how many languages and targets are supported now by both. With more open source tools for FPGA this is more feasible now than ever.

See SymbiFlow/ideas#19

XVilka commented 5 years ago

Note that after the discussion in this bug and other issues most of the people agreed to push forward the FIRRTL. Please give the feedback on this if you have any.

christiaanb commented 5 years ago

It's very unclear whether FIRRTL has asynchronous resets, so I don't know whether it can be a target.

XVilka commented 4 years ago

@christiaanb just an update, FIRRTL got an asynchronous reset, and they will be the part of the upcoming 1.2.0 release: https://github.com/freechipsproject/firrtl/issues/1196

christiaanb commented 4 years ago

@XVilka Thanks for the update, I'll check it out

XVilka commented 3 years ago

If you ever plan to add support for it, you could also check out the LLVM-based CIRCT implementation of FIRRTL as a dialect.