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clash-lang / clash-prelude

CLaSH prelude library containing datatypes and functions for circuit design
http://www.clash-lang.org/
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Prelude changes to map `Bit` to a HDL scalar type #140

Closed christiaanb closed 6 years ago

christiaanb commented 6 years ago

So instead of mapping Bit to

VHDL: std_logic_vector(0 downto 0) Verilog: wire [0:0]

We map Bit to:

VHDL: std_logic Verilog: wire