Synthesis attributes are directives passed to sythesis tools, such as Quartus. An example of such an attribute in VHDL:
attribute chip_pin : string;
attribute chip_pin of sel : signal is "C4";
attribute chip_pin of data : signal is "D1, D2, D3, D4";
This would instruct the synthesis tool to map the wire sel to pin C4, and wire data to pins D1, D2, D3, and D4. To achieve this in Clash, we add Attrs. An example of the same annotation in Clash:
import Clash.Annotations.SynthesisAttributes (Attr (..), Annotate )
myFunc
:: (Signal System Bool `Annotate` StringAttr "chip_pin" "C4")
-> (Signal System Int4 `Annotate` StringAttr "chip_pin" "D1, D2, D3, D4")
-> ...
myFunc sel data = ...
{-# NOINLINE myFunc #-}
To ensure this function will be rendered as its own module, do not forget a NOINLINE pragma.
Multiple attributes for the same argument can be specified by using a list. For example:
Synthesis attributes are directives passed to sythesis tools, such as Quartus. An example of such an attribute in VHDL:
This would instruct the synthesis tool to map the wire
sel
to pinC4
, and wiredata
to pinsD1
,D2
,D3
, andD4
. To achieve this in Clash, we addAttr
s. An example of the same annotation in Clash:To ensure this function will be rendered as its own module, do not forget a NOINLINE pragma.
Multiple attributes for the same argument can be specified by using a list. For example: