build: Bump aarch64-cpu from 9.4.0 to 10.0.0

[dependabot[bot]]

Bumps aarch64-cpu from 9.4.0 to 10.0.0.

Release notes

Sourced from aarch64-cpu's releases.

v10.0.0

Breaking

Major version bump due to tock-registers dependency - updated to 0.9 (#26)

Added

• Add automatic release pipeline (#30)

• Re-export tock-registers::interfaces::ReadWriteable (#23)

• Add register CNTHP_CTL_EL2 (#24) - "Control register for the EL2 physical timer"

• Add EL3h and EL3t fields to register SPSR_EL3 (#28)

• Add registers CNTPOFF_EL2, CPTR_EL2, HPFAR_EL2, ICC_CTLR_EL1, ICC_SRE_EL2, ICH_AP0R_EL2, ICH_AP1R_EL2, ICH_HCR_EL2, ICH_LR_EL2, ICH_MISR_EL2, ICH_VMCR_EL2, ICH_VTR_EL2, ID_AA64AFR0_EL1, ID_AA64AFR1_EL1, ID_AA64DFR0_EL1, ID_AA64DFR1_EL1, ID_AA64ISAR1_EL1, ID_AA64PFR0_EL1, ID_AA64PFR1_EL1 (#27)

• Add fields TERR, TLOR, TSW, TACR, TIDCP, TID3, BSU, FB to register HCR_EL2 (#27)

• Add fields to register ICH_LR0_EL2 (#27)

• Add field EOS to register SCTLR_EL2 (#27)

• Add fields NSA and SL0 to register VTCR_EL2 (#27)

Fixed

• Fix writing ESL_EL1 with register bitfield instead of u64 (#27)

Changelog

Sourced from aarch64-cpu's changelog.

[v10.0.0] - 2024-10-26

Breaking

Major version bump due to tock-registers dependency - updated to 0.9 (#26)

Added

• Add automatic release pipeline (#30)

• Re-export tock-registers::interfaces::ReadWriteable (#23)

• Add register CNTHP_CTL_EL2 (#24) - "Control register for the EL2 physical timer"

• Add EL3h and EL3t fields to register SPSR_EL3 (#28)

• Add registers CNTPOFF_EL2, CPTR_EL2, HPFAR_EL2, ICC_CTLR_EL1, ICC_SRE_EL2, ICH_AP0R_EL2, ICH_AP1R_EL2, ICH_HCR_EL2, ICH_LR_EL2, ICH_MISR_EL2, ICH_VMCR_EL2, ICH_VTR_EL2, ID_AA64AFR0_EL1, ID_AA64AFR1_EL1, ID_AA64DFR0_EL1, ID_AA64DFR1_EL1, ID_AA64ISAR1_EL1, ID_AA64PFR0_EL1, ID_AA64PFR1_EL1 (#27)

• Add fields TERR, TLOR, TSW, TACR, TIDCP, TID3, BSU, FB to register HCR_EL2 (#27)

• Add fields to register ICH_LR0_EL2 (#27)

• Add field EOS to register SCTLR_EL2 (#27)

• Add fields NSA and SL0 to register VTCR_EL2 (#27)

Fixed

• Fix writing ESL_EL1 with register bitfield instead of u64 (#27)

Commits

• 0a39fbd Merge pull request #27 from islet-project/main
• 9107714 Update HPFAR_EL2 and ID_AA64DFR0_EL1 fields
• 4a07a8e Merge pull request #30 from rust-embedded/feat/add-release-plz
• 66e01d9 chore(release): 🧹 Bump version
• d86c158 chore: 🧹 Format
• d10dd38 feat: ✨ Add release workflow
• e4c1f1a Merge pull request #28 from schultetwin1/add_el3h_and_el3t_to_spsr_el3
• 170ff9a Add EL3h and EL3t to SPSR_EL3
• 39369e6 Add RES1 field to MPIDR_EL1
• 193cdda Add fields to VTCR_EL2
• Additional commits viewable in compare view

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