SAMD51 NVM cache disable before write

cmaglie / FlashStorage

A convenient way to store data into Flash memory on the ATSAMD21 and ATSAMD51 processor family

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SAMD51 NVM cache disable before write #37

Closed dhalbert closed 4 years ago

dhalbert commented 4 years ago

@mitchellpontague @cmaglie

I didn't have a chance to look at #27 before it was merged. Here is one comment.

This erratum says you need to disable the NVM cache before writing to the Page Buffer, for Rev A EFP and Rev D chips. EDIT: incorrect: it's functional in our code: ~~I had misinterpreted the erratum as applicable to old Rev A chips only and had commented this out in our code. In practice I haven't seen this issue, but better safe than sorry.~~

cmaglie commented 4 years ago

Thanks @dhalbert this explains why #27 wasn't working when cache is enabled. Do you have a patch for that already?

dhalbert commented 4 years ago

There are two caches: the CMCC cache and the NVMCTRL cache. The NVMCTRL cache is enabled on reset; the CMCC cache is disabled on reset.

I'll do some testing to confirm which affects this. We are turning off the NVMCTRL cache in the UF2 bootloader before writing. We don't enable the CMCC cache in the UF2 bootloader, but we do in CircuitPython.