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cmlab / NetFPGA-1G-CML

Information about the NetFPGA 1G-CML card
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loopback test #2

Closed maryyam closed 10 years ago

maryyam commented 10 years ago

Hi all, I created the pcores by running [make] in the core directory, NetFPGA-10G-live-devel. and I changed directories to /NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml and run [make]. Would someone help me with these errors:

[root@localhost loopback_test_nf1_cml]# make make -C hw bits make[1]: Entering directory `/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw' xps -nw -scr genmakes.tcl

Xilinx Platform Studio Xilinx EDK 14.6 Build EDK_P.68d Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

XPS% Evaluating file genmakes.tcl ERROR:EDK - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_memory_mapped_lite_0 - PORT interconnect_aclk not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 46 ERROR:EDK - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_memory_mapped_lite_0 - PORT INTERCONNECT_ARESETN not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 47 ERROR:EDK - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_memory_mapped_lite_0 - PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 45 ERROR:EDK - IPNAME: bram_block, INSTANCE: microblaze_0_bram_block - BUS_INTERFACE PORTA not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 112 ERROR:EDK - IPNAME: bram_block, INSTANCE: microblaze_0_bram_block - BUS_INTERFACE PORTB not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 113 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - BUS_INTERFACE S_AXI not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 139 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PORT TX not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 140 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PORT RX not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 141 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PORT S_AXI_ACLK not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 142 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_BAUDRATE not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 133 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_DATA_BITS not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 134 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_USE_PARITY not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 135 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_ODD_PARITY not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 136 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_BASEADDR not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 137 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_HIGHADDR not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 138 ERROR:EDK - while loading XMP file make[1]: * [system.make] Error 1 make[1]: Leaving directory `/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw' make: * [all] Error 2

jmeador commented 10 years ago 
Hi -
I am attaching the log files I get when I execute the following
commands, starting in a fresh directory with nothing else. Perhaps
this will help. Please note that none of these are executed as the
root user. Here are the commands:
git clone git@github.com:cmlab/NetFPGA-10G-live.git
git checkout origin/devel -b devel. /opt/xilinx/14.6/ISE_DS/settings64.sh
cd NetFPGA-10G-live
make cml_cores
cd projects/loopback_test_nf1_cml
make
Again, note that I am not executing these commands as "root", or
using "sudo" or "su".
When you execute commands as root, your environment changes.
This may be the root cause of your problems.
Best Regards,
Jack.On 04/27/2014 05:54 AM, maryyam wrote:

  Hi all, 
    I created the pcores by running [make] in the core directory,
    NetFPGA-10G-live-devel. and I changed directories to
    /NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml and run
    [make]. Would someone help me with these errors:
  [root@localhost loopback_test_nf1_cml]# make
    make -C hw bits
    make[1]: Entering directory /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw'
      xps -nw -scr genmakes.tcl
      Xilinx Platform Studio
      Xilinx EDK 14.6 Build EDK_P.68d
      Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
      XPS% Evaluating file genmakes.tcl
      ERROR:EDK - IPNAME: axi_interconnect, INSTANCE:
      axi_interconnect_memory_mapped_lite_0 - PORT interconnect_aclk
      not found in
      the MPD -

/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 46 ERROR:EDK - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_memory_mapped_lite_0 - PORT INTERCONNECT_ARESETN not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 47 ERROR:EDK - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_memory_mapped_lite_0 - PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 45 ERROR:EDK - IPNAME: bram_block, INSTANCE: microblaze_0_bram_block - BUS_INTERFACE PORTA not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 112 ERROR:EDK - IPNAME: bram_block, INSTANCE: microblaze_0_bram_block - BUS_INTERFACE PORTB not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 113 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - BUS_INTERFACE S_AXI not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 139 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PORT TX not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 140 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PORT RX not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 141 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PORT S_AXI_ACLK not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 142 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_BAUDRATE not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 133 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_DATA_BITS not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 134 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_USE_PARITY not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 135 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_ODD_PARITY not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 136 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_BASEADDR not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 137 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_HIGHADDR not found in the MPD - /home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m hs line 138 ERROR:EDK - while loading XMP file make[1]: * [system.make] Error 1 make[1]: Leaving directory/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw' make: * [all] Error 2 — Reply to this email directly or view it on GitHub.

maryyam commented 10 years ago

Thank you for answering me. when I insert below command I get fatal error:

$ git checkout origin/devel -b devel. /opt/xilinx/14.6/ISE_DS/settings64.sh fatal: Could not switch to '/opt/xilinx/14.6/ISE_DS/' : No such file or directory

I think xilinx ---> Xilinx please help me for solving this problem.

jmeador commented 10 years ago 
Hi -
It seems like your email client may have squashed two commands
together.
Here they are again:
1) git checkout origin/devel -b devel 
2) . /opt/Xilinx/14.6/ISE_DS/settings64.sh

-- note that there is a "period" or "dot" at the beginning.
-- another way to say this is "source
/opt/Xilinx/14.6/ISE_DS/settings64.sh"
-- please make sure you are running a 64-bit OS to use this command.
-- if you are not, replace the 64 above with 32.
Yes, you are correct, the default location for the Xilinx tools is
/opt/Xilinx.
That was a typo on my part.On 05/04/2014 03:27 AM, maryyam wrote:

  Thank you for answering me.
    when I insert below command I get fatal error:
  $ git checkout origin/devel -b devel.
    /opt/xilinx/14.6/ISE_DS/settings64.sh
    fatal: Could not switch to '/opt/xilinx/14.6/ISE_DS/' : No such
    file or directory
  I think xilinx ---> Xilinx
    please help me for solving this problem.
  —
    Reply to this email directly or view
      it on GitHub.
maryyam commented 10 years ago

I run this command but I get fatal :-(

$git checkout origin/devel -b devel fatal: Cannot update paths and switch to branch 'devel' at the same time. Did you intend to checkout '.ssh/origin/devel' which can not be resolved as commit?