Closed eselahe closed 10 years ago
Hi eselahe,
The Official NetFPGA wiki contains all of the information required to setup, run, and simulate projects. We have tried to model our projects after their projects and their simulations after their simulations. The official NetFPGA wiki has an entry for simulations, it can be found here: https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA%2010G%20Simulations. Follow the directions under the section titled "Running the Simulation". Some things that aren't exactly clear from the wiki are:
The second bullet point reads as follows: "/make sure the
bashrc_addon_NetFPGA_10G is updated in your system. Check if all
variables are set in the right path. Try to run echo $NF_ROOT and
echo $NF_DESIGN_DIR and check if your directories are correct/." The
'bashrc_addon_NetFPGA_10G' is actually a file found in the root of
the NetFPGA project. You'll need to edit this file so that NF_ROOT
points to your NetFPGA repository, and that NF_DESIGN_DIR points to
the project that you're trying to test. Then, you need to source the
file before you begin tests. source bashrc_addon_NetFPGA_10G
. This
means that you'll need to update and source this file each time you
want to run tests on a different project. For example, to test the
reference_nic_nf1_cml project, my bashrc_addon_NetFPGA_10G looks
like this:
export NF_ROOT=${HOME}/devel/NetFPGA-10G-live
export NF_DESIGN_DIR=${NF_ROOT}/projects/reference_nic_nf1_cml
export NF_WORK_DIR=/tmp/${USER}
export PYTHONPATH=${NF_ROOT}/lib/python:${NF_DESIGN_DIR}/lib/Python:${NF_ROOT}/tools/scripts:
export LD_LIBRARY_PATH=${NF_ROOT}/lib/java/NetFPGAFrontEnd/bin:${LD_LIBRARY_PATH}
In response to: /In abave commands the path in "Project dir: /tmp/karin/test/reference_nic" is wrong!/
This is because you have set NF_DESIGN_DIR to point to ${NF_ROOT}/projects/reference_nic. As I mentioned above, this should be set in the bashrc_addon_NetFPGA_10G file and should be set to the project that you want to simulate. In my example, that test is the reference_nic_nf1_cml. All of the NetFPGA-1G-CML projects have 'nf1_cml' in their names.
Hope this helps, Jay
On 05/11/2014 07:17 AM, eselahe wrote:
Hello, I have configured NetFPGA as NIC, successfully. But I can't run tests successfully. For example, when I run first test,I get the below command:
[root@localhost bin]# ./nf_test.py hw --major loopback --minor maxsize Please set the environment variable 'NF_ROOT' to point to the local NetFPGA source Traceback (most recent call last): File "./nf_test.py", line 624, in identifyWorkDir() File "./nf_test.py", line 395, in identifyWorkDir project = os.path.basename(os.path.abspath(os.environ['NF_DESIGN_DIR'])) File "/usr/lib64/python2.7/UserDict.py", line 23, in getitem raise KeyError(key) KeyError: 'NF_DESIGN_DIR'
Then I set required environment variable and run test again:
[root@localhost bin]# export NF_ROOT=${HOME}/NetFPGA-10G-live [root@localhost bin]# export NF_DESIGN_DIR=${NF_ROOT}/projects/reference_nic [root@localhost bin]# ./nf_test.py hw --major loopback --minor maxsize NetFPGA environment: Root dir: /root/NetFPGA-10G-live Project name: reference_nic Project dir: /tmp/karin/test/reference_nic Work dir: /tmp/karin Root directory is /root/NetFPGA-10G-live Running global setup... PASS Running test both_loopback_maxsize... /tmp/karin/test/reference_nic/both_loopback_maxsize/run.py --hw exited with value 1 FAIL Output was: Traceback (most recent call last): File "/tmp/karin/test/reference_nic/both_loopback_maxsize/run.py", line 3, in from NFTest import * ImportError: No module named NFTest
Running global teardown... PASS
In abave commands the path in "Project dir: /tmp/karin/test/reference_nic" is wrong!
How can I run these tests, successfully?
Thanks.
— Reply to this email directly or view it on GitHub https://github.com/cmlab/NetFPGA-1G-CML/issues/5.
Hi, Thanks for your answering. I solved above problem by get help of your answer. But I can't run any test, again. Because I get below errors:
[root@localhost bin]# ./nf_test.py sim --major loopback --minor maxsize NetFPGA environment: Root dir: /home/karin/NetFPGA-10G-live Project name: reference_nic_nf1_cml Project dir: /tmp/karin/test/reference_nic_nf1_cml Work dir: /tmp/karin make: Entering directory `/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test' Makefile:43: system_incl.make: No such file or directory echo exit|xps -nw system.xmp
Xilinx Platform Studio Xilinx EDK 14.6 Build EDK_P.68d Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
XPS% Loading xmp file system.xmp ERROR:EDK - IPNAME: bram_block, INSTANCE: microblaze_0_bram_block - BUS_INTERFACE PORTA not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 139 ERROR:EDK - IPNAME: bram_block, INSTANCE: microblaze_0_bram_block - BUS_INTERFACE PORTB not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 140 ERROR:EDK - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0 - PORT interconnect_aclk not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 245 ERROR:EDK - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0 - PORT INTERCONNECT_ARESETN not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 246 ERROR:EDK - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0 - PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 244 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232 - BUS_INTERFACE S_AXI not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 258 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232 - PORT S_AXI_ACLK not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 259 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232 - PORT TX not found in the MPD
XPS% make: *\ No rule to make target __xps/simgen.opt', needed by
axi_model'. Stop.
make: Leaving directory `/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test'
512
=== Work directory is /tmp/karin/test/reference_nic_nf1_cml
=== Setting up test in /tmp/karin/test/reference_nic_nf1_cml/both_loopback_maxsize
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_0_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_0_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_0_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_1_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_1_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_1_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_2_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_2_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_2_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_3_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_3_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_3_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/dma_0_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/dma_0_expected.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/reg_stim.log’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/reg_expect.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/reg_stim.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system_axisim.mhs’: No such file or directory
=== Running test /tmp/karin/test/reference_nic_nf1_cml/both_loopback_maxsize ... using cmd ['/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/both_loopback_maxsize/run.py', '--sim', 'vsim']
Please help me, again.
Thanks, elahe
I'm not sure how to reproduce what you're seeing. I would suggest going to /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/ and from there doing a git checkout .
to make sure that any modified files are back to their original state. Then a git clean -xdf .
to cleanup any other generated files. Be sure to include the 'dot' in the previous commands so that they only work on the directory that you're in. I would then try the nf_test command again. Also, if you plan on using isim to simulate, you might want to add the --isim flag to the nf_test command. Also, if you want the GUI interface for isim, then also attach the --gui flag. This information is in the nf_test help section. Run ./nf_test.py -h
to see it.
Hi, I followed your instructions in above comment. But I couldn't run tests, successfully :-(
[root@localhost bin]# ./nf_test.py sim --major loopback --minor maxsize --isim --gui NetFPGA environment: Root dir: /home/karin/NetFPGA-10G-live Project name: reference_nic_nf1_cml Project dir: /tmp/karin/test/reference_nic_nf1_cml Work dir: /tmp/karin cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/hw/pcores/’: No such file or directory make: Entering directory `/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test' Makefile:43: system_incl.make: No such file or directory echo exit|xps -nw system.xmp
Xilinx Platform Studio Xilinx EDK 14.6 Build EDK_P.68d Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
XPS% Loading xmp file system.xmp Created pcores directory ERROR:EDK - IPNAME: bram_block, INSTANCE: microblaze_0_bram_block - BUS_INTERFACE PORTA not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 139 ERROR:EDK - IPNAME: bram_block, INSTANCE: microblaze_0_bram_block - BUS_INTERFACE PORTB not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 140 ERROR:EDK - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0 - PORT interconnect_aclk not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 245 ERROR:EDK - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0 - PORT INTERCONNECT_ARESETN not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 246 ERROR:EDK - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0 - PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 244 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232 - BUS_INTERFACE S_AXI not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 258 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232 - PORT S_AXI_ACLK not found in the MPD - /home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system.mhs line 259 ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232 - PORT TX not found in the MPD
XPS% make: *\ No rule to make target __xps/simgen.opt', needed by
axi_model'. Stop.
make: Leaving directory `/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test'
512
=== Work directory is /tmp/karin/test/reference_nic_nf1_cml
=== Setting up test in /tmp/karin/test/reference_nic_nf1_cml/both_loopback_maxsize
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_0_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_0_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_0_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_1_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_1_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_1_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_2_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_2_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_2_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_3_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_3_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/nf1_cml_interface_3_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/dma_0_log.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/dma_0_expected.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/reg_stim.log’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/reg_expect.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/reg_stim.axi’: No such file or directory
cp: cannot stat ‘/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/system_axisim.mhs’: No such file or directory
=== Running test /tmp/karin/test/reference_nic_nf1_cml/both_loopback_maxsize ... using cmd ['/home/karin/NetFPGA-10G-live/projects/reference_nic_nf1_cml/test/both_loopback_maxsize/run.py', '--sim', 'isim', '--gui']
And for a hardware test:
[root@localhost bin]# ./nf_test.py hw --major loopback --minor maxsize
NetFPGA environment:
Root dir: /home/karin/NetFPGA-10G-live
Project name: reference_nic_nf1_cml
Project dir: /tmp/karin/test/reference_nic_nf1_cml
Work dir: /tmp/karin
Root directory is /home/karin/NetFPGA-10G-live
Running global setup... PASS
Running test both_loopback_maxsize... /tmp/karin/test/reference_nic_nf1_cml/both_loopback_maxsize/run.py --hw exited with value 1
FAIL
Output was:
WARNING: No route found for IPv6 destination :: (no default route?)
loading the nf10_lib library..
Traceback (most recent call last):
File "/tmp/karin/test/reference_nic_nf1_cml/both_loopback_maxsize/run.py", line 3, in
Running global teardown... PASS
Help Me Please! Thanks in advance.
Hello, I have configured NetFPGA as NIC, successfully. But I can't run tests successfully. For example, when I run first test,I get the below command:
[root@localhost bin]# ./nf_test.py hw --major loopback --minor maxsize Please set the environment variable 'NF_ROOT' to point to the local NetFPGA source Traceback (most recent call last): File "./nf_test.py", line 624, in
identifyWorkDir()
File "./nf_test.py", line 395, in identifyWorkDir
project = os.path.basename(os.path.abspath(os.environ['NF_DESIGN_DIR']))
File "/usr/lib64/python2.7/UserDict.py", line 23, in getitem
raise KeyError(key)
KeyError: 'NF_DESIGN_DIR'
Then I set required environment variable and run test again:
[root@localhost bin]# export NF_ROOT=${HOME}/NetFPGA-10G-live [root@localhost bin]# export NF_DESIGN_DIR=${NF_ROOT}/projects/reference_nic [root@localhost bin]# ./nf_test.py hw --major loopback --minor maxsize NetFPGA environment: Root dir: /root/NetFPGA-10G-live Project name: reference_nic Project dir: /tmp/karin/test/reference_nic Work dir: /tmp/karin Root directory is /root/NetFPGA-10G-live Running global setup... PASS Running test both_loopback_maxsize... /tmp/karin/test/reference_nic/both_loopback_maxsize/run.py --hw exited with value 1 FAIL Output was: Traceback (most recent call last): File "/tmp/karin/test/reference_nic/both_loopback_maxsize/run.py", line 3, in
from NFTest import *
ImportError: No module named NFTest
Running global teardown... PASS
In abave commands the path in "Project dir: /tmp/karin/test/reference_nic" is wrong!
How can I run these tests, successfully?
Thanks.