Top-level VHDL written by scripts now:
1) Instantiates all memories of given type & bit-width within the nonant in a "generate" loop.
2) Instantiates all signals in nonant connected to memories of given type & bit-width as an array, where array is indexed by enum. The definitions of these arrays and enums is written to a VHDL package memUtil_pkg.vhd.
3) Adds option "-x" to generate_hdl.py, which causes top-level VHDL to have additional output ports giving data of intermediate memories in chain.
Top-level VHDL written by scripts now: 1) Instantiates all memories of given type & bit-width within the nonant in a "generate" loop. 2) Instantiates all signals in nonant connected to memories of given type & bit-width as an array, where array is indexed by enum. The definitions of these arrays and enums is written to a VHDL package memUtil_pkg.vhd. 3) Adds option "-x" to generate_hdl.py, which causes top-level VHDL to have additional output ports giving data of intermediate memories in chain.
N.B. The top-level VHDL written by the updated scripts in this PR and the updated VHDL test-bench they require can be found in https://github.com/cms-L1TK/firmware-hls/pull/144 .