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cms-L1TK / project_generation_scripts

Python scripts to generate the wiring map of the tracklet pattern recognition & the top-level HDL that calls the HLS modules in the Hybrid Chain.
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Fix TE-TC chain #20

Closed fatimayousuf closed 3 years ago

fatimayousuf commented 3 years ago

This PR allows us to run the Tracket Engine-Tracklet Calculator chain.

Most errors were due to the fact that the Tracklet Calculator puts some modules in arrays, which threw errors in generating the top-level file.

Some commands I used for testing this:

I then looked at the top level file and confirmed that all the needed modules were there.

rzouCERN commented 3 years ago

@fatimayousuf Did you test the code with an up-to-date master of firmware_hls? I just tried with current master of firmware_hls and I got the following warnings when I included TC in the run:

./generator_hdl.py ../firmware-hls_v0 -p processingmodules.dat -m memorymodules.dat -w wires.dat --uut TE_L3PHIC12_L4PHIC22 -u 0 -d 1
Info in <TCanvas::Print>: pdf file TrackletProject.pdf has been created
matchArgPortNames_TC: Unknown argument AllStubMemory<InnerRegion<Seed>
matchArgPortNames_TC: Unknown argument AllStubMemory<InnerRegion<Seed>
matchArgPortNames_TC: Unknown argument AllStubMemory<InnerRegion<Seed>
matchArgPortNames_TC: Unknown argument AllStubMemory<InnerRegion<Seed>
matchArgPortNames_TC: Unknown argument AllStubMemory<InnerRegion<Seed>
fatimayousuf commented 3 years ago

@fatimayousuf Did you test the code with an up-to-date master of firmware_hls? I just tried with current master of firmware_hls and I got the following warnings when I included TC in the run:

./generator_hdl.py ../firmware-hls_v0 -p processingmodules.dat -m memorymodules.dat -w wires.dat --uut TE_L3PHIC12_L4PHIC22 -u 0 -d 1
Info in <TCanvas::Print>: pdf file TrackletProject.pdf has been created
matchArgPortNames_TC: Unknown argument AllStubMemory<InnerRegion<Seed>
matchArgPortNames_TC: Unknown argument AllStubMemory<InnerRegion<Seed>
matchArgPortNames_TC: Unknown argument AllStubMemory<InnerRegion<Seed>
matchArgPortNames_TC: Unknown argument AllStubMemory<InnerRegion<Seed>
matchArgPortNames_TC: Unknown argument AllStubMemory<InnerRegion<Seed>

@rzouCERN Sorry about that! The code should work now for the current version of the firmware_hls repo

tomalin commented 3 years ago

Please check that the TE-TC SectorProcessor.vhd can be synthesised, (proving that it is valid VHDL), by using commands 1,2,3 & 6 from the "Running chains" section of https://github.com/cms-L1TK/firmware-hls/blob/master/README.md . You'll need small changes to cope with TE-TC, and fact you don't have VHDL test-bench. (Mei-Li has this working for IR-VMR chain, so can advise).

meisonlikesicecream commented 3 years ago

Please check that the TE-TC SectorProcessor.vhd can be synthesised, (providing that it is valid VHDL), by using commands 1,2,3 & 6 from the "Running chains" section of https://github.com/cms-L1TK/firmware-hls/blob/master/README.md . You'll need small changes to cope with TE-TC, and fact you don't have VHDL test-bench. (Mei-Li has this working for IR-VMR chain, so can advise).

I have it working for the VMR only. The missing implementation for external LUT ports in the IR does not allow me to synthesise it for the IR :-)

tomalin commented 3 years ago

The conflicts above are due to other people making changes to "master" since you created your branch. To fix this, please update your branch with the latest changes to master. I think this requires (assuming you already checked out your branch):

  1. Back up your code, in case git messes up
  2. git pull
  3. git rebase origin/master . This may flag up conflicts that you need to fix by hand.
  4. Check that your local directory contains a merge of your changes and other peoples.
  5. git diff --stat --cached origin/reduced_config (check what you will push)
  6. git push --force-with-lease origin reduced_config
rzouCERN commented 3 years ago

All conflicts resolved. Top level synthesizes with ./generator_hdl.py ../firmware-hls_v0 -p processingmodules.dat -m memorymodules.dat -w wires.dat --uut TE_L3PHIC12_L4PHIC22 -u 0 -d 0 and ./generator_hdl.py ../firmware-hls_v0 -p processingmodules.dat -m memorymodules.dat -w wires.dat --uut TC_L1L2E -u 1 -d 0.

Needs https://github.com/cms-L1TK/firmware-hls/pull/158.

tomalin commented 3 years ago

Please add to README.md, the example command "./generator_hdl.py ../firmware-hls --uut TC_L1L2E -u 1 -d 0" (or whatever your preferred TE-TC chain is).

tomalin commented 3 years ago

As a future improvement (not required for this PR), consider declaring the signals "TEbendinnertable" etc. as an array, with an enumerated index; and also instantiating all the work.tf_lut entities inside a "generate" loop. This will make the VHDL more compact.

rzouCERN commented 3 years ago

I've added an TE-TC example to Readme, removed unnecessary check on the memModule and moved the checking of "table" in argname to its own if statement. I also fixed the IPname of the TE module so that it includes the seed info (e.g. TE_L1L2 instead of just TE) since we will have a unique TE for every seed. I've checked again the top level it generates and it still passes synthesis.

tomalin commented 3 years ago

As a future improvement (not required for this PR), consider declaring the signals "TEbendinnertable" etc. as an array, with an enumerated index; and also instantiating all the work.tf_lut entities inside a "generate" loop. This will make the VHDL more compact.

I've created an issue https://github.com/cms-L1TK/project_generation_scripts/issues/25 to remind us of this "to do".