cms-L1TK / project_generation_scripts

Python scripts to generate the wiring map of the tracklet pattern recognition & the top-level HDL that calls the HLS modules in the Hybrid Chain.
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Update memory bit widths #22

Closed tomalin closed 3 years ago

tomalin commented 3 years ago

1) Andrew had updated the memory bit widths in SectorProcessor.vhd, during the FW sync, but had not yet made the corresponding change to the python scripts that generate this file. This fix addresses that. 2) This fix also removes the 1 clock delay in generating the "start" signals in SectorProcessor.vhd, which we were concerned about. But this doesn't affect discrepancies.