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cms-L1TK / project_generation_scripts

Python scripts to generate the wiring map of the tracklet pattern recognition & the top-level HDL that calls the HLS modules in the Hybrid Chain.
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Project generation script generate illegal VHDL #33

Closed pwittich closed 2 years ago

pwittich commented 3 years ago

In the code here and elsewhere in the summer chain in the memUtil_pkg.vhd file the following piece of code is generated.

  type enum_DL_39 is (PS10G_1_A,PS10G_2_A,PS10G_2_B,PS10G_3_A,PS10G_3_B,PS_1_A,PS_1_B,PS_2_A,PS_2_B,2S_1_A,2S_1_B,2S_2_A,2S_2_B,2S_3_A,2S_3_B,2S_4_A,2S_4_B);

i.e., types which start with "2S". This is not legal VHDL ; a simple fix would be to just replace "2S" with "TWOS" or something, but a cursory glance in the code did not make it obvious to me where to put this fix.

The test bench for the IR-VMR chain doesn't run into this issue; it looks like it just is looking at PS fibers from PS modules and hence this problem didn't show up.

tomalin commented 2 years ago

Issue solved by https://github.com/cms-L1TK/project_generation_scripts/pull/34