cms-L1TK / project_generation_scripts

Python scripts to generate the wiring map of the tracklet pattern recognition & the top-level HDL that calls the HLS modules in the Hybrid Chain.
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Fix issue that VHDL variables cant start with number #34

Closed tomalin closed 2 years ago

tomalin commented 2 years ago

1) Fixes issue https://github.com/cms-L1TK/project_generation_scripts/issues/33 .

2) Also fixes issue that TrackWord & StubWords from created from a TrackFitMemory all have the same memory.index, so when the code sorts the memories by this index, their order is random. This avoids the issue that the order of these items in memUtils.vhd changed randomly when one modified unrelated parts of the python scripts.