I've tried it for the summer chain as well. It creates the tb, but I get errors when trying to run the simulation in Vivado. Did not look further into this.
Known weaknesses: it doesn't use 16 bins for VMSME in the disk. I.e. it uses the default 8 bins.
Added implementation for generating testbenches. It works for the "standard" IRVMR, TETC, PRMEMC chains as well as a single ME. Examples of the testbenches can be seen here: https://github.com/meisonlikesicecream/firmware-hls/tree/me_vhdl_tb/IntegrationTests
I've tried it for the summer chain as well. It creates the tb, but I get errors when trying to run the simulation in Vivado. Did not look further into this.
Known weaknesses: it doesn't use 16 bins for VMSME in the disk. I.e. it uses the default 8 bins.