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cms-L1TK / project_generation_scripts

Python scripts to generate the wiring map of the tracklet pattern recognition & the top-level HDL that calls the HLS modules in the Hybrid Chain.
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Fix to FIFOs in test-bench #39

Closed tomalin closed 2 years ago

tomalin commented 2 years ago

Two fixes to the VHDL test-bench:

1) The signals for the FIFO interface were buggy, being those of a BRAM. Now fixed. 2) The concatenated track+stub output from the TrackBuilder, needed to compare with the emData/ file has been added.

After this is merged, the ir_phibinword_update branch will be rebased on top of it.

N.B. To be consistent with these changes, one change is required in the HLS repo: FileWriterFIFO.vhd must be edited to delete its (unnecesary) dependence on the START signal.

aehart commented 2 years ago

I think this looks good.

Regarding the bodges, I guess the way to resolve these is to split up the test vectors that are output by the emulation? So that instead of a single file for each seed (e.g., TrackFit_TF_L1L2_04.dat), there would be separate files for the track word and each of the matched stub words. If you agree, I can prepare a PR for the emulation with this change.

tomalin commented 2 years ago

I think this looks good.

Regarding the bodges, I guess the way to resolve these is to split up the test vectors that are output by the emulation? So that instead of a single file for each seed (e.g., TrackFit_TF_L1L2_04.dat), there would be separate files for the track word and each of the matched stub words. If you agree, I can prepare a PR for the emulation with this change.

I agree that splitting these would eliminate the ugly bodge, so would be wise if it doesn't cause too many headaches. So too would replacing the "TrackFit" memory in emData/LUTs/memorymodules.dat by the TW & BW memories.