update for new binned memories and first split-fpga chain

cms-L1TK / project_generation_scripts

Python scripts to generate the wiring map of the tracklet pattern recognition & the top-level HDL that calls the HLS modules in the Hybrid Chain.

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update for new binned memories and first split-fpga chain #57

Closed jasonfan393 closed 5 months ago

jasonfan393 commented 5 months ago

PR (corresponding with firmware_hls 315 adds capability to handle new binned memory module. An additional flag is added to generator_hdl.py to enable the creation of a first half split-fpga chain. This chain is from IR to TP, and excludes the VMSME and TPROJ memories that will instead be calculated on the second device.