[ ] Bug fix (non-breaking change which fixes an issue)
[X] New feature (non-breaking change which adds functionality)
[ ] Breaking change (fix or feature that would cause existing functionality to change)
Motivation and Context
Connectivity testing requires link monitoring. Also require tools for phase scanning and programming GBT that can bypass the "address table hack" on the CTP7 (to get around the out of memory issue).
How Has This Been Tested?
(py2.7) [dorney@gem904qc8daq]~/scratch0/CMS_GEM/CMS_GEM_DAQ/vfatqc-python-scripts% testConnectivity.py -m 5 --shelf=2 -s5 --skipDACScan --skipScurve -o 0x1 -d --nPhaseScans=50 -o 0x1
Open pickled address table if available /opt/cmsgemos/etc/maps/amc_address_table_top.pickle...
Initializing AMC gem-shelf02-amc05
====================
Step 1: Checking GBT Communication
====================
Checking GBT Communication (Before Programming GBTs)
--=======================================--
-> GEM SYSTEM GBT INFORMATION
--=======================================--
----------OH0----------
GBT0.READY 1
GBT0.NOT_READY 0
GBT0.RX_HAD_OVERFLOW 0
GBT0.RX_HAD_UNDERFLOW 0
GBT1.READY 1
GBT1.NOT_READY 0
GBT1.RX_HAD_OVERFLOW 0
GBT1.RX_HAD_UNDERFLOW 0
GBT2.READY 1
GBT2.NOT_READY 0
GBT2.RX_HAD_OVERFLOW 0
GBT2.RX_HAD_UNDERFLOW 0
Programming GBTs
Checking GBT Communication (After Programming GBTs)
--=======================================--
-> GEM SYSTEM GBT INFORMATION
--=======================================--
----------OH0----------
GBT0.READY 1
GBT0.NOT_READY 0
GBT0.RX_HAD_OVERFLOW 0
GBT0.RX_HAD_UNDERFLOW 0
GBT1.READY 1
GBT1.NOT_READY 0
GBT1.RX_HAD_OVERFLOW 0
GBT1.RX_HAD_UNDERFLOW 0
GBT2.READY 1
GBT2.NOT_READY 0
GBT2.RX_HAD_OVERFLOW 0
GBT2.RX_HAD_UNDERFLOW 0
GBT Communication Established
And then phase scans:
====================
Step 4: Checking VFAT Communication
====================
Checking GBT Communication (After Programming FPGA)
--=======================================--
-> GEM SYSTEM GBT INFORMATION
--=======================================--
----------OH0----------
GBT0.READY 1
GBT0.NOT_READY 0
GBT0.RX_HAD_OVERFLOW 0
GBT0.RX_HAD_UNDERFLOW 0
GBT1.READY 1
GBT1.NOT_READY 0
GBT1.RX_HAD_OVERFLOW 0
GBT1.RX_HAD_UNDERFLOW 0
GBT2.READY 1
GBT2.NOT_READY 0
GBT2.RX_HAD_OVERFLOW 0
GBT2.RX_HAD_UNDERFLOW 0
GBT Communication Is Stil Good
Scanning GBT Phases, this may take a moment please be patient
Phase VFAT0 VFAT1 VFAT2 VFAT3 VFAT4 VFAT5 VFAT6 VFAT7 VFAT8 VFAT9 VFAT10 VFAT11 VFAT12 VFAT13 VFAT14 VFAT15 VFAT16 VFAT17 VFAT18 VFAT19 VFAT20 VFAT21 VFAT22
VFAT23
------- ------- ------- ------- ------- ------- ------- ------- ------- ------- ------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -
-------
0 50 50 50 50 50 50 0 50 50 50 50 0 50 50 50 50 50 50 50 50 50 50 50
50
1 50 50 50 50 50 50 50 50 50 50 50 50 0 50 50 50 50 50 50 50 50 50 0
50
2 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50
50
3 50 50 50 50 50 50 50 50 50 50 50 50 50 50 0 50 50 0 50 50 50 50 50
50
4 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50
50
5 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50
50
6 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 0 50 50 50 50 50 50
50
7 50 50 50 50 50 50 50 0 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50
50
8 0 50 50 50 50 50 50 50 50 50 50 0 11 50 50 50 50 50 50 50 50 50 50
50
9 50 50 50 50 50 50 50 50 0 50 50 50 50 0 50 50 50 50 50 50 50 50 50
50
10 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 0
50
11 50 50 50 50 50 50 50 50 50 50 50 50 50 50 0 50 50 50 50 50 50 50 50
50
12 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50
50
13 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50
14 50 50 46 50 50 50 50 50 50 50 50 50 50 50 50 50 41 50 50 50 50 50 50 50
15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Found good phase, writing phase 1 to (OH0,VFAT0)
Found good phase, writing phase 1 to (OH0,VFAT1)
Found good phase, writing phase 1 to (OH0,VFAT2)
Found good phase, writing phase 1 to (OH0,VFAT3)
Found good phase, writing phase 1 to (OH0,VFAT4)
Found good phase, writing phase 1 to (OH0,VFAT5)
Found good phase, writing phase 2 to (OH0,VFAT6)
Found good phase, writing phase 1 to (OH0,VFAT7)
Found good phase, writing phase 1 to (OH0,VFAT8)
Found good phase, writing phase 1 to (OH0,VFAT9)
Found good phase, writing phase 1 to (OH0,VFAT10)
Found good phase, writing phase 2 to (OH0,VFAT11)
Found good phase, writing phase 3 to (OH0,VFAT12)
Found good phase, writing phase 1 to (OH0,VFAT13)
Found good phase, writing phase 1 to (OH0,VFAT14)
Found good phase, writing phase 1 to (OH0,VFAT15)
Found good phase, writing phase 1 to (OH0,VFAT16)
Found good phase, writing phase 1 to (OH0,VFAT17)
Found good phase, writing phase 1 to (OH0,VFAT18)
Found good phase, writing phase 1 to (OH0,VFAT19)
Found good phase, writing phase 1 to (OH0,VFAT20)
Found good phase, writing phase 1 to (OH0,VFAT21)
Found good phase, writing phase 3 to (OH0,VFAT22)
Found good phase, writing phase 1 to (OH0,VFAT23)
Checklist:
[x] My code follows the code style of this project.
[ ] My change requires a change to the documentation.
Description
Provides functionality for:
Makes use of code from https://github.com/cms-gem-daq-project/reg_utils/pull/42 by @lpetre-ulb
Requires: https://github.com/cms-gem-daq-project/ctp7_modules/pull/82
Types of changes
Motivation and Context
Connectivity testing requires link monitoring. Also require tools for phase scanning and programming GBT that can bypass the "address table hack" on the CTP7 (to get around the out of memory issue).
How Has This Been Tested?
And then phase scans:
Checklist: