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cnrv / RISCV-East-Asia-Biweekly-Sync

Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
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Notes on CHISEL/FIRRTL #1

Open sequencer opened 3 years ago

sequencer commented 3 years ago

目前Chisel/FIRRTL社区比较冷清 我提议是对RocketChip进行拆包后，添加文档测试，学习LLVM的优良传统，确定依赖，添加文档，可以upstream的upstream，不能的部分，自己作为Upstream进行持续维护，目前我正在推进多个工具进标准库：

  1. Clock-domain-crossing
    • AsyncQueue: architecture, verification.
    • FIRRTL clock domain annotation: CircuitGraph, Clock-Domain-Analysis
  2. Decoder API
  3. Verification API
    • SVA Property emission
    • FPGA synthesis Verification
    • Verilator integration
  4. diploamcy API
    • Architecture documentation
    • User documentation
    • UnitTest

在本次的双周会上我会拖一遍代码进行介绍。 贡献者能力要求：

  1. Scala
  2. FIRRTL Framework
  3. ASIC/FPGA experience

我会同步Chisel Dev的讨论到中国社区。可以指导相关的代码实现，可以Review PR。

lazyparser commented 3 years ago

great!

yqszxx commented 3 years ago

终于蹲到一个自己满足能力要求又想做的项目了😂dalao带我一个！

SihaoLiu commented 3 years ago

太好了，加我一个😀

sequencer commented 3 years ago

AsyncQueue, prev-knowledges: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf Verification: http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

sequencer commented 3 years ago

Update: @yqszxx 领取Decoder chipsalliance/chisel3#1737.