how to run rocket-chip in other board (KC705)

[stwjt]

I want to know how to modify this project to run rocket-chip in other board (KC705). I have modified the chiptop.v and aximem.v and some constraints but it seems to difficult to handle the ddr3. So I want to know the difficulty degree to adapt this project to the the board for a raw recruit.

[wsong83]

I think this is doable and the difficulty level is medium. Two suggestions:

• Look at the KC705 port of lowRISC as you can find how DDR is connected there. I would suggest to look at the untethered-v0.2 branch at https://github.com/lowRISC/lowrisc-chip/tree/untether-v0.2, and https://github.com/lowRISC/lowrisc-kc705/tree/f6230bdbe4c6305fcf10d027961cc8120ee4312c
• Look at the nexys-video branch at this repo as I have just port the design to Nexys-Video board. https://github.com/cnrv/fpga-rocket-chip/tree/nexys-video

[stwjt]

I think this is doable and the difficulty level is medium. Two suggestions:

• Look at the KC705 port of lowRISC as you can find how DDR is connected there. I would suggest to look at the untethered-v0.2 branch at https://github.com/lowRISC/lowrisc-chip/tree/untether-v0.2, and https://github.com/lowRISC/lowrisc-kc705/tree/f6230bdbe4c6305fcf10d027961cc8120ee4312c
• Look at the nexys-video branch at this repo as I have just port the design to Nexys-Video board. https://github.com/cnrv/fpga-rocket-chip/tree/nexys-video

thanks. It is very helpful to me.

[TwistsOfFate]

@stwjt Did you succeed in running rocket-chip on KC705? I'm also trying to port to KC705 but couldn't get any output from the UART so far. I've done the following:

• Modified DDR and SPI ports in chip_top.v and AXIMem.v, so that they are the same as https://github.com/lowRISC/lowrisc-chip/blob/untether-v0.2/src/main/verilog/chip_top.sv
• Modified constraints file to something like https://github.com/lowRISC/lowrisc-kc705/blob/f6230bdbe4c6305fcf10d027961cc8120ee4312c/constraint/pin_plan.xdc
• Reconfigured DDR memory controller according to https://github.com/lowRISC/lowrisc-kc705/blob/f6230bdbe4c6305fcf10d027961cc8120ee4312c/script/mig_config.prj
• Changed DDR_SIZE in sdload.c to 1GB

Is there something I'm missing?

[wsong83]

Please note that this repo does not fully match with the kc705 port in lowRISC. Simply copying code and parameters may not do the job. You need to understand the configurations, especially for DDR and the clock network.

[stwjt]

@stwjt Did you succeed in running rocket-chip on KC705? I'm also trying to port to KC705 but couldn't get any output from the UART so far. I've done the following:

• Modified DDR and SPI ports in chip_top.v and AXIMem.v, so that they are the same as https://github.com/lowRISC/lowrisc-chip/blob/untether-v0.2/src/main/verilog/chip_top.sv
• Modified constraints file to something like https://github.com/lowRISC/lowrisc-kc705/blob/f6230bdbe4c6305fcf10d027961cc8120ee4312c/constraint/pin_plan.xdc
• Reconfigured DDR memory controller according to https://github.com/lowRISC/lowrisc-kc705/blob/f6230bdbe4c6305fcf10d027961cc8120ee4312c/script/mig_config.prj
• Changed DDR_SIZE in sdload.c to 1GB

Is there something I'm missing?

那个我不会用github啊 我现在就是128mb可以 但我懒得开1GB了 我要怎么联系你啊

[TwistsOfFate]

@stwjt Did you succeed in running rocket-chip on KC705? I'm also trying to port to KC705 but couldn't get any output from the UART so far. I've done the following:

• Modified DDR and SPI ports in chip_top.v and AXIMem.v, so that they are the same as https://github.com/lowRISC/lowrisc-chip/blob/untether-v0.2/src/main/verilog/chip_top.sv
• Modified constraints file to something like https://github.com/lowRISC/lowrisc-kc705/blob/f6230bdbe4c6305fcf10d027961cc8120ee4312c/constraint/pin_plan.xdc
• Reconfigured DDR memory controller according to https://github.com/lowRISC/lowrisc-kc705/blob/f6230bdbe4c6305fcf10d027961cc8120ee4312c/script/mig_config.prj
• Changed DDR_SIZE in sdload.c to 1GB

Is there something I'm missing?

那个我不会用github啊 我现在就是128mb可以 但我懒得开1GB了 我要怎么联系你啊

谢谢！可以邮件联系 fanqi.yu@outlook.com

[stwjt]

UART does not have the output because we used the pin_plan.xdc of lowrisc project . Rst_top is defined in this file, but rst_top was not pressed.

[TwistsOfFate]

Thanks to your help, I have done porting the hardware to a KC705 board. The changes are recorded here: https://github.com/TwistsOfFate/fpga-rocket-chip/tree/kc705

[wsong83]

nice work!