Closed SivaMounikaPeddineni closed 5 years ago
The synthesis has already failed which means there is no point to go further to implementation. From the error message of synthesis, it looks like you did not correctly generate the clock converter (a Xilinx IP block) for the design, otherwise it should not be recognized as a blackblox.
Thanks for your response. We will work on it
Close. Reopen if needed.
When tried to generate the bit stream below error is encountered at the implementation stage. Error: [Opt 31-430] Found a FDRE that its data pin is undriven. Driver is required to prevent unexpected behavior:mmio/peri_Xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_no_arbiter.m_mesg_i_reg[46].
Please find the attached image for critical warning details. Kindly, help us to resolve this issue.