marlonjames
commented
4 years ago This looks to be the culprit:
# ** Error (suppressible): (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.
ModelSim uses FLI to access VHDL.
Closed Fatsie closed 3 years ago
marlonjames
commented
4 years ago This looks to be the culprit:
# ** Error (suppressible): (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.
ModelSim uses FLI to access VHDL.
themperek
commented
4 years ago @Fatsie Please close if the issue is solved.
github-actions[bot]
commented
3 years ago Has your question been resolved? If so please close this issue. If it has not been resolved, you may need to provide more information. If no more activity on this issue occurs in 7 days, it will be closed.
stdefeber
commented
1 year ago This issue is not as dead as it appears. I have a similar issue. However this involves xcelium.
OS : CentOs 7.6 CoCoTb : 1.6.2 Xcelium : 21.03.008
We switched from having mostly VHDL as top and intermediate layers to verilog/SV. When a VHDL module is compiled into a library, CoCoTb can not find it anymore.
Loading snapshot worklib.tb_top:v .................... Done
xmsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
-.--ns INFO cocotb.gpi ..mbed/gpi_embed.cpp:110 in set_program_name_in_venv Using Python virtual environment interpreter at /data/home/<user>/projects/sandbox/cocotb_sandbox/.venv/bin/python
-.--ns INFO cocotb.gpi ../gpi/GpiCommon.cpp:99 in gpi_print_registered_impl VPI registered
-.--ns INFO cocotb.gpi ../gpi/GpiCommon.cpp:99 in gpi_print_registered_impl VHPI registered
xcelium> source /cadappl/ictools/cadence_xcelium/21.03.008/tools/xcelium/files/xmsimrc
xcelium> run
0.00ns DEBUG Reopened stderr with line buffering
0.00ns DEBUG Reopened stdout with line buffering
0.00ns INFO Running on xmsim(64) version 21.03-s008
0.00ns INFO Running tests with cocotb v1.6.2 from /data/home/<user>/projects/sandbox/cocotb_sandbox/.venv/lib64/python3.8/site-packages/cocotb
0.00ns INFO Seeding Python random module with 1680872851
0.00ns DEBUG Looking for root handle 'tb_top' over 2 implementations
0.00ns DEBUG Got a Root handle (tb_top) back from VPI
0.00ns DEBUG Checking tb_top exists
0.00ns DEBUG Created
0.00ns DEBUG Python Path: ,/opt/rh/rh-python38/root/usr/lib64/python38.zip,/opt/rh/rh-python38/root/usr/lib64/python3.8,/opt/rh/rh-python38/root/usr/lib64/python3.8/lib-dynload,/data/home/<user>l/projects/sandbox/cocotb_sandbox/.venv/lib64/python3.8/site-packages,/data/home/<user>/projects/sandbox/cocotb_sandbox/.venv/lib/python3.8/site-packages,/data/home/<user>/projects/sandbox/cocotb_sandbox/python/src
0.00ns DEBUG PWD: /data/home/<user>/projects/sandbox/cocotb_sandbox/cocotb
0.00ns INFO Found test test.test01_access
0.00ns INFO running test01_access (1/1)
0.00ns INFO Info message
0.00ns INFO @ get_top
0.00ns INFO @ get_top
0.00ns DEBUG Searching for u_ic
0.00ns DEBUG Checking if u_ic is native through implementation VPI
0.00ns DEBUG VPI: Created GPI object from type vpiModule(32)
0.00ns DEBUG Found u_ic via VPI
0.00ns DEBUG Checking tb_top.u_ic exists
0.00ns DEBUG Created
0.00ns DEBUG Searching for u_top
0.00ns DEBUG Checking if u_top is native through implementation VPI
0.00ns DEBUG VPI: Created GPI object from type vpiModule(32)
0.00ns DEBUG Found u_top via VPI
0.00ns DEBUG Checking tb_top.u_ic.u_top exists
0.00ns DEBUG Created
tb_top.u_ic.u_top
0.00ns INFO @ get_dff
0.00ns INFO @ get_core
0.00ns INFO @ get_top
0.00ns INFO @ get_top
0.00ns DEBUG Searching for u_core
0.00ns DEBUG Checking if u_core is native through implementation VPI
0.00ns DEBUG VPI: Created GPI object from type vpiModule(32)
0.00ns DEBUG Found u_core via VPI
0.00ns DEBUG Checking tb_top.u_ic.u_top.u_core exists
0.00ns DEBUG Created
0.00ns DEBUG Searching for u_sub_wrapper
0.00ns DEBUG Checking if u_sub_wrapper is native through implementation VPI
0.00ns WARNING VPI: Not able to map type vhpiCompInstStmtK(1024) to object.
0.00ns DEBUG Unable to fetch object tb_top.u_ic.u_top.u_core.u_sub_wrapper
0.00ns DEBUG Checking if u_sub_wrapper is native through implementation VHPI
0.00ns DEBUG VHPI: Creating tb_top:u_ic:u_top:u_core:u_sub_wrapper of type 2 (vhpiCompInstStmtK)
0.00ns DEBUG Found u_sub_wrapper via VHPI
0.00ns DEBUG Checking tb_top.u_ic.u_top.u_core.u_sub_wrapper exists
0.00ns DEBUG Created
0.00ns DEBUG Searching for u_sub
0.00ns DEBUG Checking if u_sub is native through implementation VPI
0.00ns DEBUG Unable to query vpi_get_handle_by_name tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub
0.00ns DEBUG Checking if u_sub is native through implementation VHPI
0.00ns DEBUG VHPI: Unable to query vhpi_handle_by_name tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub
0.00ns DEBUG Failed to find a handle named u_sub via any registered implementation
0.00ns INFO test01_access failed
Traceback (most recent call last):
File "/data/home/<user>/projects/sandbox/cocotb_sandbox/cocotb/test.py", line 49, in test01_access
sub_wrapper.u_sub._discover_all()
File "/data/home/<user>/projects/sandbox/cocotb_sandbox/.venv/lib64/python3.8/site-packages/cocotb/handle.py", line 346, in __getattr__
raise AttributeError(f"{self._name} contains no object named {name}")
AttributeError: u_sub_wrapper contains no object named u_sub
0.00ns INFO **************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
**************************************************************************************
** test.test01_access FAIL 0.00 0.00 0.04 **
**************************************************************************************
** TESTS=1 PASS=0 FAIL=1 SKIP=0 0.00 0.01 0.01 **
**************************************************************************************
0.00ns DEBUG VHPI: Releasing VhpiObjHdl handle for tb_top.u_ic.u_top.u_core.u_sub_wrapper at 0x500040
I have anonymized the above output. Therefor \<user>.
The Makefile:
CURDIR=$(realpath .)
TOPLEVEL := tb_top
COCOTBMAKEDIR=$(shell cocotb-config --makefiles)
VHDL_SOURCES_module_lib := \
$(CURDIR)/../RTL/dff.m.vhdl \
$(CURDIR)/../INTERFACE/sub.e.vhdl \
$(CURDIR)/../RTL/sub.a.vhdl
VHDL_SOURCES := \
$(CURDIR)/../RTL/sub_wrapper.vhdl \
VERILOG_SOURCES := \
$(CURDIR)/../RTL/core.sv \
$(CURDIR)/../RTL/ic.sv \
$(CURDIR)/../RTL/top.sv \
$(CURDIR)/../TESTBENCH/tb_top.v
VHDL_LIB_ORDER = \
module_lib \
export COCOTB_LOG_LEVEL=DEBUG
TOPLEVEL_LANG=verilog
MODULE=test
SIM=xcelium
COCOTB_HDL_TIMEUNIT=100fs
COCOTB_HDL_TIMEPRECISION=100fs
COCOTB_RESOLVE_X=ZEROS
COMPILE_ARGS += -v93 -V200X -accessreg +rwc $(INCDIRS)
include $(COCOTBMAKEDIR)/Makefile.inc
include $(COCOTBMAKEDIR)/Makefile.simTestcase:
test.py
import cocotb
from cocotb.triggers import Timer
import logging
logger = logging.getLogger('simple_test')
logger.setLevel (logging.INFO)
def get_ic(dut):
logger.info("@ get_top")
return dut.u_ic
def get_top(dut):
logger.info("@ get_top")
return get_ic(dut).u_top
def get_core(dut):
logger.info("@ get_core")
return get_top(dut).u_core
def get_sub_wrapper(dut):
logger.info("@ get_dff")
return get_core(dut).u_sub_wrapper
def get_sub(dut):
logger.info("@ get_dff")
return get_sub_wrapper(dut).u_sub
def get_dff0(dut):
logger.info("@ get_dff")
return get_sub(dut).u_dff0
def get_dff1(dut):
logger.info("@ get_dff")
return get_top(dut).u_dff1
@cocotb.test()
def test01_access(dut):
"""
"""
logger.debug ('Debug message')
logger.info ('Info message')
#dut.u_top.core.dff._discover_all()
top = get_top(dut)
print(top)
sub_wrapper = get_sub_wrapper(dut)
sub_wrapper.u_sub._discover_all()
print(sub_wrapper)
dff0 = get_dff0(dut)
#dff1 = get_dff1(dut)
print(dff0)
My apologies for the eleaborate hierarchy. It mimics the real design and was to find out whether it had anything to do with the number of levels.
Test bench, not used as such, just to mimic the real example. In the real design it contains pull-ups e.q. I2C :
tb_top.v
module tb_top(
input clk,
input d0,
output q0,
input d1,
output q1
);
ic u_ic (
.clk(clk),
.q0(q0),
.d0(d0),
.q1(q1),
.d1(d1)
);
endmoduleIC-level:
ic.sv
module ic(
clk,
d0,
q0,
d1,
q1
);
input clk, d0, d1;
output q0, q1;
top u_top(
.clk(clk),
.q0(q0),
.d0(d0)
);
endmoduleTop:
top.sv
module top(
clk,
d0,
q0
);
input clk, d0;
output q0;
core u_core(
.clk(clk),
.q(q0),
.d(d0)
);
endmoduleThe core:
core.sv
module core(clk, d, q);
input clk, d;
output q;
sub u_sub_wrapper(.clk(clk), .q(q), .d(d));
endmodule
I had created a sub_wrapper just to find out whether a VHDL module in library "work" would solve the issue.
sub_wrapper.vhdl
library ieee;
use ieee.std_logic_1164.all;
library module_lib;
use module_lib.all;
entity sub_wrapper is
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity;
architecture rtl of sub_wrapper is
begin
u_sub : entity module_lib.sub
port map (
clk => clk,
d => d,
q => q
);
end rtl;The sub architecture itself:
sub.a.vhdl
library ieee;
use ieee.std_logic_1164.all;
library module_lib;
use module_lib.all;
architecture rtl of sub is
begin
u_dff0 : entity module_lib.dff
port map (
clk => clk,
d => d,
q => q
);
end rtl;
The sub entity:
sub.e.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity sub; And finally a dff:
dff.m.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity dff;
architecture rtl of dff is
begin
process(clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
end architecture rtl;A work around has been found. When all sources are marked as VHDL_SOURCES it works.
VHDL_SOURCES_module_lib := \
$(CURDIR)/../RTL/dff.m.vhdl \
$(CURDIR)/../INTERFACE/sub.e.vhdl \
$(CURDIR)/../RTL/sub.a.vhdl
VHDL_SOURCES := \
$(CURDIR)/../RTL/sub_wrapper.vhdl \
$(CURDIR)/../RTL/core.sv \
$(CURDIR)/../RTL/ic.sv \
$(CURDIR)/../RTL/top.sv \
$(CURDIR)/../TESTBENCH/tb_top.v
0.00ns INFO Found test test.test01_access
0.00ns INFO running test01_access (1/1)
0.00ns INFO Info message
0.00ns INFO @ get_top
0.00ns INFO @ get_top
0.00ns DEBUG Searching for u_ic
0.00ns DEBUG Checking if u_ic is native through implementation VPI
0.00ns DEBUG VPI: Created GPI object from type vpiModule(32)
0.00ns DEBUG Found u_ic via VPI
0.00ns DEBUG Checking tb_top.u_ic exists
0.00ns DEBUG Created
0.00ns DEBUG Searching for u_top
0.00ns DEBUG Checking if u_top is native through implementation VPI
0.00ns DEBUG VPI: Created GPI object from type vpiModule(32)
0.00ns DEBUG Found u_top via VPI
0.00ns DEBUG Checking tb_top.u_ic.u_top exists
0.00ns DEBUG Created
tb_top.u_ic.u_top
0.00ns INFO @ get_dff
0.00ns INFO @ get_dff
0.00ns INFO @ get_dff
0.00ns INFO @ get_core
0.00ns INFO @ get_top
0.00ns INFO @ get_top
0.00ns DEBUG Searching for u_core
0.00ns DEBUG Checking if u_core is native through implementation VPI
0.00ns DEBUG VPI: Created GPI object from type vpiModule(32)
0.00ns DEBUG Found u_core via VPI
0.00ns DEBUG Checking tb_top.u_ic.u_top.u_core exists
0.00ns DEBUG Created
0.00ns DEBUG Searching for u_sub_wrapper
0.00ns DEBUG Checking if u_sub_wrapper is native through implementation VPI
0.00ns WARNING VPI: Not able to map type vhpiCompInstStmtK(1024) to object.
0.00ns DEBUG Unable to fetch object tb_top.u_ic.u_top.u_core.u_sub_wrapper
0.00ns DEBUG Checking if u_sub_wrapper is native through implementation VHPI
0.00ns DEBUG VHPI: Creating tb_top:u_ic:u_top:u_core:u_sub_wrapper of type 2 (vhpiCompInstStmtK)
0.00ns DEBUG Found u_sub_wrapper via VHPI
0.00ns DEBUG Checking tb_top.u_ic.u_top.u_core.u_sub_wrapper exists
0.00ns DEBUG Created
0.00ns DEBUG Searching for u_sub
0.00ns DEBUG Checking if u_sub is native through implementation VPI
0.00ns WARNING VPI: Not able to map type vhpiCompInstStmtK(1024) to object.
0.00ns DEBUG Unable to fetch object tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub
0.00ns DEBUG Checking if u_sub is native through implementation VHPI
0.00ns DEBUG VHPI: Creating tb_top:u_ic:u_top:u_core:u_sub_wrapper:u_sub of type 2 (vhpiCompInstStmtK)
0.00ns DEBUG Found u_sub via VHPI
0.00ns DEBUG Checking tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub exists
0.00ns DEBUG Created
0.00ns DEBUG Searching for u_dff0
0.00ns DEBUG Checking if u_dff0 is native through implementation VPI
0.00ns WARNING VPI: Not able to map type vhpiCompInstStmtK(1024) to object.
0.00ns DEBUG Unable to fetch object tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub.u_dff0
0.00ns DEBUG Checking if u_dff0 is native through implementation VHPI
0.00ns DEBUG VHPI: Creating tb_top:u_ic:u_top:u_core:u_sub_wrapper:u_sub:u_dff0 of type 2 (vhpiCompInstStmtK)
0.00ns DEBUG Found u_dff0 via VHPI
0.00ns DEBUG Checking tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub.u_dff0 exists
0.00ns DEBUG Created
tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub.u_dff0
0.00ns DEBUG Searching for clk
0.00ns DEBUG Checking if clk is native through implementation VPI
0.00ns WARNING VPI: Not able to map type vhpiPortDeclK(1079) to object.
0.00ns DEBUG Unable to fetch object tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub.u_dff0.clk
0.00ns DEBUG Checking if clk is native through implementation VHPI
0.00ns DEBUG VHPI: Detected a LOGIC type tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub.u_dff0.clk
0.00ns DEBUG VHPI: Creating tb_top:u_ic:u_top:u_core:u_sub_wrapper:u_sub:u_dff0:clk of type 5 (vhpiEnumTypeDeclK)
0.00ns DEBUG Found clk via VHPI
0.00ns DEBUG Checking tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub.u_dff0.clk exists
0.00ns DEBUG Created
0.00ns DEBUG clk has 1 elements
10.00ns DEBUG Searching for d
10.00ns DEBUG Checking if d is native through implementation VPI
10.00ns WARNING VPI: Not able to map type vhpiPortDeclK(1079) to object.
10.00ns DEBUG Unable to fetch object tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub.u_dff0.d
10.00ns DEBUG Checking if d is native through implementation VHPI
10.00ns DEBUG VHPI: Detected a LOGIC type tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub.u_dff0.d
10.00ns DEBUG VHPI: Creating tb_top:u_ic:u_top:u_core:u_sub_wrapper:u_sub:u_dff0:d of type 5 (vhpiEnumTypeDeclK)
10.00ns DEBUG Found d via VHPI
10.00ns DEBUG Checking tb_top.u_ic.u_top.u_core.u_sub_wrapper.u_sub.u_dff0.d exists
10.00ns DEBUG Created
10.00ns DEBUG d has 1 elements
70.00ns INFO test01_access passed
70.00ns INFO **************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
**************************************************************************************
** test.test01_access PASS 70.00 0.01 10970.02 **
**************************************************************************************
** TESTS=1 PASS=1 FAIL=0 SKIP=0 70.00 0.01 6107.54 **
**************************************************************************************
Nabih-Saleh
commented
6 months ago unfortunately, this work around does not always work!, because it complain when compiling .v file because it found illegal syntax based on vhdl compiler
This may be related to #1004 and #1105 but there signal was accessed in verilog module from VHDL top. My problem may also be missing feature due to use of 32 bit Modelsim delivered with Quartus software.
dff.vhdl:
top.v:
test.py:
Makefile:
Running it (second time so no compiling is done):
When I remove
dut.dff._discover_all()from test.py; the simulation passes without segfault.