Error loading shared library C;C (Riviera-PRO)

[LeChuck42]

I'm trying to run the examples after installing cocotb. I followed the installation instructions.

Installed versions (running on Win10 x64):

• conda 4.12.0
• cocotb 1.6.2
• python 3.10.4 (from conda)
• Riviera-PRO 2021.10.114.8313 (x64)

Error Log:

(cocotb) PS C:\pld\cocotb\examples\mixed_language\tests> make SIM=riviera
/usr/bin/make -f Makefile results.xml
make[1]: Entering directory '/c/pld/cocotb/examples/mixed_language/tests'
mkdir -p sim_build
set -o pipefail; GPI_EXTRA=C:/Users/***/Miniconda3/envs/cocotb/lib/site-packages/cocotb/libs/cocotbvhpi_aldec.dll:cocotbvhpi_entry_point TOPLEVEL_LANG=verilog \
MODULE=test_mixed_language TESTCASE= TOPLEVEL=endian_swapper_mixed  /c/Aldec/Riviera-PRO-2021.10-x64/bin/vsimsa  -do sim_build/runsim.tcl | tee sim_build/sim.log
# Aldec, Inc. Riviera-PRO version 2021.10.114.8313 built for Windows64 on October 29, 2021.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2021 Aldec, Inc. All rights reserved.
onerror {
        puts [read [open sim.log r]]
        quit -code 1
}
alib sim_build/work
# ALIB: Library "work" attached.
# work = C:/pld/cocotb/examples/mixed_language/tests/sim_build/work/work.lib
set worklib sim_build/work
# LIBRARY MANAGER: Error: Library "sim_build/work" not found.
# sim_build/work
acom  -dbg C:/pld/cocotb/examples/mixed_language/hdl/endian_swapper.vhdl
# ACOM: File: C:/pld/cocotb/examples/mixed_language/hdl/endian_swapper.vhdl
# ACOM: Compile Entity "endian_swapper_vhdl"
# ACOM: Compile Architecture "impl" of Entity "endian_swapper_vhdl"
# ACOM: Compile success 0 Errors 0 Warnings  Analysis time :  16.0 [ms]
alog -timescale 1ns/1ps  +define+COCOTB_SIM -dbg -pli libgpi C:/pld/cocotb/examples/mixed_language/hdl/endian_swapper.sv C:/pld/cocotb/examples/mixed_language/hdl/toplevel.sv
# ALOG: Pass 1. Scanning modules hierarchy.
# ALOG: Info: VCP2113 Module endian_swapper_vhdl found in current working library.
# ALOG: Pass 2. Processing instantiations.
# ALOG: Info: VCP2876 C:/pld/cocotb/examples/mixed_language/hdl/toplevel.sv : (67, 64): Implicit net declaration, symbol csr_waitrequest_sv has not been declared in module endian_swapper_mixed.
# ALOG: Info: VCP2876 C:/pld/cocotb/examples/mixed_language/hdl/toplevel.sv : (97, 66): Implicit net declaration, symbol csr_waitrequest_vhdl has not been declared in module endian_swapper_mixed.
# ALOG: Pass 3. Processing behavioral statements.
# ALOG: ELB/DAG code generating.
# ALOG: Unit top modules: endian_swapper_mixed.
# ALOG: $root top modules: endian_swapper_mixed.
# ALOG: Compile success 0 Errors 0 Warnings  Analysis time: 0[s].
# ALOG: done
asim   +access +w -interceptcoutput -O2 -dbg -pli C:/Users/***/Miniconda3/envs/cocotb/lib/site-packages/cocotb/libs/cocotbvpi_aldec.dll endian_swapper_mixed
# ELBREAD: Elaboration process.
# ELBREAD: Elaboration time 0.2 [s].
# KERNEL: Main thread initiated.
# KERNEL: Kernel process initialization phase.
# ELAB2: Elaboration final pass...
# KERNEL: PLI/VHPI kernel's engine initialization done.
# PLI: Loading library 'C:\Users\***\Miniconda3\envs\cocotb\lib\site-packages\cocotb\libs\cocotbvpi_aldec.dll'
# COUT:      -.--ns ERROR    cocotb.gpi                         ..s\cocotb_utils.cpp:56   in utils_dyn_open                  Unable to open lib C;C: The specified module could not be found.
# COUT:
# COUT: cocotb: Error loading shared library C;C
# VSIM: Fatal Error: The simulator process terminated unexpectedly.
# VSIM: Error: Simulation initialization failed.
# SCRIPTER: sim_build/runsim.tcl : (12, 1): Executing onerror command.
# SCRIPTER: Error: Unknown error occurred during simulation.
puts [read [open sim.log r]]
# SCRIPTER: Error: couldn't open "sim.log": no such file or directory
ERROR: results.xml was not written by the simulation!
/c/Users/***/Miniconda3/envs/cocotb/lib/site-packages/cocotb/share/makefiles/simulators/Makefile.riviera:146: recipe for target 'results.xml' failed
make[1]: *** [results.xml] Error 1
make[1]: Leaving directory '/c/pld/cocotb/examples/mixed_language/tests'
C:\Users\***\Miniconda3\envs\cocotb\lib\site-packages\cocotb\share\makefiles/Makefile.inc:39: recipe for target 'sim' failed
make: *** [sim] Error 2

[marlonjames]

This is the same problem from #2941. Both are Windows + conda. One is Riviera, the other is Questa.

[LeChuck42]

This is apparently some path conversion when calling vsimsa from sh

GPI_EXTRA inside vsimsa: C;C:\Users\***\Miniconda3\envs\cocotb\Library\Users\***\Miniconda3\envs\cocotb\lib\site-packages\cocotb\libs\cocotbvhpi_aldec.dll;cocotbvhpi_entry_point

Some tests:

> set TEST=C:/Testing:foobar
> echo %TEST%
C:/Testing:foobar
> vsimsa -do "echo $::env(TEST)"
# Aldec, Inc. Riviera-PRO version 2021.10.114.8313 built for Windows64 on October 29, 2021.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2021 Aldec, Inc. All rights reserved.
# C:/Testing:foobar

> sh
sh-4.3$ echo $TEST
C:/Testing:foobar
sh-4.3$ vsimsa -do "echo $::env(TEST)"
# Aldec, Inc. Riviera-PRO version 2021.10.114.8313 built for Windows64 on October 29, 2021.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2021 Aldec, Inc. All rights reserved.
# C;C:\Users\***\Miniconda3\envs\cocotb\Library\Testing;foobar

When using backslashes the conversion doesn't trigger:

> set TEST2=C:\Testing:foobar
> sh
sh-4.3$ vsimsa -do "echo $::env(TEST2)"
# Aldec, Inc. Riviera-PRO version 2021.10.114.8313 built for Windows64 on October 29, 2021.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2021 Aldec, Inc. All rights reserved.
# C:\Testing:foobar

[marlonjames]

Thanks for figuring that out!

Is that sh you are running from a conda package?

[NicolasFrankel]

This is apparently some path conversion when calling vsimsa from sh

GPI_EXTRA inside vsimsa: C;C:\Users\***\Miniconda3\envs\cocotb\Library\Users\***\Miniconda3\envs\cocotb\lib\site-packages\cocotb\libs\cocotbvhpi_aldec.dll;cocotbvhpi_entry_point

Some tests:

> set TEST=C:/Testing:foobar
> echo %TEST%
C:/Testing:foobar
> vsimsa -do "echo $::env(TEST)"
# Aldec, Inc. Riviera-PRO version 2021.10.114.8313 built for Windows64 on October 29, 2021.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2021 Aldec, Inc. All rights reserved.
# C:/Testing:foobar

> sh
sh-4.3$ echo $TEST
C:/Testing:foobar
sh-4.3$ vsimsa -do "echo $::env(TEST)"
# Aldec, Inc. Riviera-PRO version 2021.10.114.8313 built for Windows64 on October 29, 2021.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2021 Aldec, Inc. All rights reserved.
# C;C:\Users\***\Miniconda3\envs\cocotb\Library\Testing;foobar

When using backslashes the conversion doesn't trigger:

> set TEST2=C:\Testing:foobar
> sh
sh-4.3$ vsimsa -do "echo $::env(TEST2)"
# Aldec, Inc. Riviera-PRO version 2021.10.114.8313 built for Windows64 on October 29, 2021.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2021 Aldec, Inc. All rights reserved.
# C:\Testing:foobar

So, as the result: did you run successfully your script? Did you add some changes in make or other files?

[LeChuck42]

Is that sh you are running from a conda package?

Yes, correct.

So, as the result: did you run successfully your script? Did you add some changes in make or other files?

I switch to another system running Linux, avoiding the issue.

[NicolasFrankel]

Thanks for figuring that out!

Is that sh you are running from a conda package?

Could you tell me please, may I add described above changes into necessary files (and which one) for successful compilation?

[ktbarrett]

This seems like a Riviera-PRO issue isn't it? The variable in sh is fine, but in Riviera it's screwed up. My guess is Riviera sees it's on Windows running from a POSIX shell then decides to convert the variable, which it assumes is a PATH-like variable from POSIX shell, into Windows style PATH-like. Maybe they should only be doing that on specific variables and not all of them...

[xwzheng1020]

I met the same issue. I try to hardcode the path in GpiCommon.cpp:

        if (strlen(lib_env) >= 2 && lib_env[1] == ';')
        {
            // only available for my computer and verilog-vhdl situation
            lib_list = "C:/ProgramData/Anaconda3/lib/site-packages/cocotb/libs/cocotbfli_modelsim.dll:cocotbfli_entry_point";
            printf("new GPI_EXTRA: %s\n", lib_list.c_str());
        }

it is ugly but seems to be ok.

[github-actions[bot]]

Has your question been resolved? If so please close this issue. If it has not been resolved, you may need to provide more information. If no more activity on this issue occurs in 7 days, it will be closed.

[LeChuck42]

This has not yet been solved afaik. If it won't be fixed, maybe it should at least be noted in the documentation (installation instructions)?

[ktbarrett]

I think it was auto-closed because the question label wasn't removed once it was confirmed to be an issue. I can reopen it, but it would be nice to know what exactly the problem is and what this repo can do to solve it. From the above comments it seems like it's an issue with either Riviera or msys2's make or sh, so I'm not sure what can be done here. As for documenting the problem, this issue serves as documentation.