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cocotb / cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
https://www.cocotb.org
BSD 3-Clause "New" or "Revised" License
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Awaiting `Timer` in ReadOnly phase not legal? #3967

Open ktbarrett opened 5 days ago

ktbarrett commented 5 days ago

VHDL-2019 LRM 21.3.6.8 vhpiCbRepEndOfTimeStep

It is an error if a vhpiCbEndOfTimeStep or vhpiCbRepEndOfTimeStep callback causes activity on a driver or a signal (see 14.7.3.1) or registers or enables a vhpiCbAfterDelay, vhpiCbRepAfterDelay, vhpiCbTimeout, or vhpiCbRepTimeOut callback.

SystemVerilog 2017 LRM 38.36.2

cbReadOnlySynch Callback shall occur the same as for cbReadWriteSynch, except that writing values or scheduling events before the next scheduled event is not allowed.

_Originally posted by @marlonjames in https://github.com/cocotb/cocotb/pull/3942#discussion_r1649798481_

This needs investigation. We may need to prevent this case if this doesn't work in some simulators.