Verilog & VHDL based Mixed Design with UVM Testbench not Working in Synopsys VCS

cocotb / cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

BSD 3-Clause "New" or "Revised" License

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Actually, I am trying to run an environment having mixed design files (Verilog & VHDL) with UVM based testbench on Synopsys VCS. My Make_file includes following commands:

vlogan -work work +v2k +incdir+$(UVM_HOME) $(UVM_HOME)/uvm_pkg.sv +libext+.sv -f ./results/vlog_flist.f -ntb_opts uvm-1.2 -full64 -debug_all vhdlan -work work -f ./results/vhdl_flist.f vcs -timescale=1ns/1ps -f ./results/build_uvc.f -error=noZONMCM -ntb_opts uvm-1.2 -sverilog -cm line+cond+tgl+fsm -ova_cov -cm_hier config_covg.cfg -cm_name ${TEST} -LDFLAGS -Wl,--no-as-needed -debug_all

All the design files are parsed but the vcs could not be able to find the instantiated Design in Testbench top file.

cocotb / cocotb

Verilog & VHDL based Mixed Design with UVM Testbench not Working in Synopsys VCS #4187