Specify exact variation of RISC-V specification emulated by Codewars in the docs

[DonaldKellett]

Depends on #438

RISC-V is a highly modular ISA, meaning it is comprised of a base ISA with many optional extensions. Currently, the language version for RISC-V specifies "RV64" which is too vague. Multiple sources suggest that the QEMU RISC-V emulator implements the RV64GC specification:

• https://qemu-project.gitlab.io/qemu/system/riscv/virt.html - this is for the RISC-V virt board in full system emulation but probably applies to user-mode emulation as well
• https://osblog.stephenmarz.com/ch1.html

Details on the full range of base + extension ISAs defined can be found in the official specification.

[kazk]

Yeah, I wasn't sure which extensions were supported. I'll update Codewars once we find out. RV64IMACFD might be more clear instead of using the G shorthand, but that might be too long. RV64GC will fit better.