Closed Mark-Platts closed 3 years ago
That is correct, but naturally depends on the size of the instruction. After reading an instruction, IP is incremented once. That occurs at the top of the while loop before we enter the switch block.
If it is in fact a one-byte instruction, IP is already pointing at the correct place since the next byte in memory is the next instruction.
If it's a two-byte instruction, then presumably the memory gets read again and the IP should get incremented again after that.
If it's a three-byte instruction, then you read two additional bytes in memory and so IP should be incremented twice.
I don't think there are any four-byte instructions but I'm sure you can see how the pattern continues.
Basically, by the end of the case statement, IP should be pointing at the next unused byte in memory.
Ahh, just saw the edit. Good stuff. Can I confirm you DON'T want this merged for now? If that's the case it would be best to prefix the name with WIP or something so it's clear it's not ready.
Cheers, I just wanted to be sure that the cpu doesn't do that bit itself before reading the next instruction, but then I realised it would be silly to do it that way because it would interfere with things like JMP.
I don't mind if this is merged since the instruction is complete. I'll have the testing done in a few mins though so I'll update the PR.
Testing complete. Seems to do everything it should! Ready for merge now.
The code of the test appears to say AND #$FF but the comment says AND #$00. I'm guessing you meant the former?
My mistake, I tested a few different operands but forgot to update the comment part. The comment should be #$FF as of the last test I did.
I'll amend and push that if you would like. :P
Might as well start as we mean to continue :)
There we go!
I plan to come back in a bit and test this.
Just wanted to show you and make sure I understood: When an operation does something internal and then moves on (i.e. doesn't explicitly mess with the IP), should that operation then IP++ ready for the CPU to read the next instruction? It seems that way from the other examples, I just wanted to check.
Edit: I've answered the question now :P