Fairly low priority, but there are a bunch of CPU quirks that don't seem to be correctly emulated right now from what I can tell:
W65C02S comes with a bunch of NOPs, and their cycle and byte counts vary. They can be checked from the W65C02S datasheet (https://www.westerndesigncenter.com/wdc/documentation/w65c02s.pdf, Caveats, table 7-1). The current approach of generating tables doesn't really lend itself well for this and results in them all being 1 byte and 2 cycles.
RMW instructions (like ASL mem, LSR mem...) don't do one read, they do two reads (read the same byte in twice) and write the modified byte back once. These matter when performing RMW ops on memory-mapped I/O registers (VERA has those at least). (in NMOS 6502, it did one read and two writes.)
JMP indirect should add +1 cycle if the address is $xxFF. (This extra cycle fixes the high byte which would be wrong in NMOS 6502).
Indexed access across page boundary not only adds a cycle, but does an extra read of the last instruction byte.
Combined with existing bugs there could be quite a bit of work. Maybe the alternative is rewriting the CPU emulation entirely. I once found a source for (NMOS?) 6502 describing what each cycle of each opcode did, but I don't know if anyone has documented the same for the W65C02S.
ziplantil
commented
1 year ago
Fairly low priority, but there are a bunch of CPU quirks that don't seem to be correctly emulated right now from what I can tell:
Combined with existing bugs there could be quite a bit of work. Maybe the alternative is rewriting the CPU emulation entirely. I once found a source for (NMOS?) 6502 describing what each cycle of each opcode did, but I don't know if anyone has documented the same for the W65C02S.