Closed mooinglemur closed 1 year ago
This is currently a placeholder for some changes that are being proposed upstream in VERA code.
https://github.com/fvdhoef/vera-module/pull/32
There might be a handful of minor changes that will happen in the proposed Verilog (such as a range check), but the general idea is mirrored in the emu in this PR.
This is currently a placeholder for some changes that are being proposed upstream in VERA code.
https://github.com/fvdhoef/vera-module/pull/32
There might be a handful of minor changes that will happen in the proposed Verilog (such as a range check), but the general idea is mirrored in the emu in this PR.