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commanderx16 / x16-rom

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State of YM2151 #308

Open akumanatt opened 2 years ago

akumanatt commented 2 years ago

I'm reporting here since there seems to be no repository for reporting hardware issues. Currently, YM2151 can't be read reliably at a full 8 MHz bus clock which is too fast. This means that its busy flag and timer interrupts are pretty much useless, considering its IRQ line is connected to the system and VIA#2 could be eliminated this way.

There is a way to work around this by pulling 65C02's RDY pin low when accessing it until a read is guaranteed, which could be done by only one IC.

Also, are you sure you can really source them in big volume or accept yet another FPGA replacement? I and other people in the community are afraid if it's going to be pulled at the last minute. We are definitely not letting this to happen for the third time...

ZeroByteOrg commented 2 years ago

For anyone reading this issue - the community has worked with Kevin to create a clock stretching circuit for the X16 that slows down the clock whenever the YM2151 CS line goes low, which allows reads to happen successfully. The slight delay between writing an address and writing the data register is still un-stretched so code needs to make sure that enough time passes between these writes.