Closed cycyucheng1010 closed 1 week ago
I am not sure why DIOXilinxPlacedOverlay is not found. It is located here: https://github.com/comparch-security/chipyard-random-llc/blob/master/fpga/fpga-shells/src/main/scala/shell/xilinx/GPIOXilinxOverlay.scala
@fems2991
This seems to be related with a treadle incompatability issue and should be fixed by the latest commit 4c657d0d0e013d79ee68fec8c26c0398ff9614bc
Dear @wsong83 Thank you for your reply. I have learned a lot about the clever design choices implemented in the Genesys2 code. However, I am curious whether it is necessary to modify the SiFive block when designing a Genesys2 FPGA board with features similar to the Chipyard VCU118, such as Ethernet and UART. Additionally, could you recommend any useful reference materials for someone currently working on FPGA board implementation?
Best Regards Rick Chen
The whole modification to the original Chipyard was finished by my student @fems2991 who has now graduated. In other words, I am not in a position to give detailed advice. General speaking, you do not need to revise peripheral IPs such as Ethernet or UART.The implementation of these are normally standardized (in a sense that drivers are already available in Linux kernel). Normally what you need to do is related to configure (connect) the peripheral IPs to the processor using the existing code in Chipyard.
Hello,
During my experiments with the Chipyard FFT generator, I noticed that your lab has also experimented with the Genesys2 for on-board testing. We referred to your Genesys2 code, but encountered an issue that we couldn't resolve. Could you please provide some advice?
Version: Chipyard 1.8.1
Error log: /GENESYS2newShell.scala:126:11: not found: type DIOXilinxPlacedOverlay [error] extends DIOXilinxPlacedOverlay(name, designInput, shellInput)