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comparch-security / spike-cache

Spike with a coherence supported cache model
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number of L1 caches do not match ncore error #1

Closed th0ma5b closed 1 year ago

th0ma5b commented 1 year ago

Hi @wsong83,

I am trying to use your cache model to simulate a single 32KB cache with 64 set, 2 ways, 32B line. But when running it I get this error: "The number of L1 caches 1 do not match with the number of core 1."

Can your model support such config: "config": { "L1_64x2" : ["1x64x2"], }, "cache": { "1x64x2": { "base": "1x64x8", "way": 2 }, ...

It also fails for all already specified configs with L1 cache number = 1, such as "L2_1024x16_LRU" in cache_model/config/cache.json.

it fails here: https://github.com/comparch-security/spike-cache/blob/c63c26856fc91afb9214e2fec74731e894d659e6/spike_main/spike.cc#L217:L218

if(ccfg.enable[0] && ccfg.number[0] != nprocs * 2) {
  fprintf(stderr, "The number of L1 caches %d do not match with the number of cores %ld\n", ccfg.number[0], nprocs);

Is ccfg.number[0] the number of L1 caches? Why should ccfg.number[0] be twice nprocs?

Best regards

wsong83 commented 1 year ago

Spike-cache currently assumes that the number of L1 caches is always 2 times the number of cores: one for instruction and one for data.

Why do you want to have a Spike simulation with only one L1 cache?

If what you want is simply a simultion of a cache, the cache model can run in standalone mode where you just need to feed the model with a read/write trace.

th0ma5b commented 1 year ago

Hi wsong, Thank you for replying so quick. Oh, for some reason I did not realized that "number" was covering both I and D caches. That's clear now. So if I understand correctly the cache model is not only for Spike. Spike must always have "number" set to 2 for L1. I guess this means I cache and D cache are always configured in the same way in this model. Is it possible to model different I cache and D cache configuration? 谢谢

wsong83 commented 1 year ago

You can if you are willing to modify the code related to the initialization of cache model in Spike. The configuration file is there for users to set up cache models easily.

Sorry I did not figure out a way to describe this (supporting different I and D L1 cache configuration) in the configuration file yet. The existing way of describing thing is already clumsy anyway and we are planning to have a refactoring if time allows in the future. The cache model and Spike can support it almost naturally.