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concurrencykit / ck

Concurrency primitives, safe memory reclamation mechanisms and non-blocking (including lock-free) data structures designed to aid in the research, design and implementation of high performance concurrent systems developed in C99+.
http://concurrencykit.org/
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AArch64 LSE support. #86

Closed akopytov closed 7 years ago

akopytov commented 7 years ago

Add a new configure option, --enable-lse, which is only effective for the AArch64 architecture. When used, most ckpr* atomics will use Large System Extensions instructions as per the ARMv8.1 specification, rather then LL/SC instruction pairs.

cognet commented 7 years ago

Hi !

That does look good to me, thanks a lot ! Just one minor thing : any reason you manually assign registers for the cas_2 variant ? Is it because the compiler isn't smart enough (yet) to deal correctly with the cas/casp instructions ?

akopytov commented 7 years ago

Hi Olivier!

Yes, the manual assignment is needed, because the specification has rather unusual requirements for the registers in the CASP instruction:

<Xs> is the 64-bit general register to be compared and loaded, encoded in the “Rs” field. Xs must be an even numbered register.
<X(s+1)> is the second 64-bit general register to be compared and loaded

<Xt> is the 64-bit general register to be conditionally stored, encoded in the “Rt” field. Xt must be an even numbered register.
<X(t+1)> is the second 64-bit general register to be conditionally stored