conneroisu processsor-proj-1 issues

conneroisu / processsor-proj-1

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#86 github-actions[bot] opened 6 hours ago
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new ALU tests with all operations for part 2cVIII

#85 DanielMauricio13 closed 19 hours ago
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[Part 3] In your writeup, show the Modelsim output for each of the following tests, and provide a discussion of result correctness. It may be helpful to also annotate the waveforms directly.

#84 aidanfoss closed 1 day ago
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fix control unit

#83 aidanfoss closed 1 day ago
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#82 github-actions[bot] closed 6 hours ago
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modified ALU working fine now

#81 DanielMauricio13 closed 1 day ago
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ALU

#80 DanielMauricio13 closed 1 day ago
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Update tb_barrelShifter.vhd

#79 aidanfoss closed 2 days ago
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testing barrelshifter, final fix

#78 aidanfoss closed 2 days ago
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should really just gitignore this file

#77 aidanfoss closed 2 days ago
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70 merge damage

#76 aidanfoss closed 2 days ago
1
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#75 github-actions[bot] closed 1 day ago
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[Part 2 (b.i)] What are the control flow possibilities that your instruction fetch logic must support? Describe these possibilities as a function of the different control flow-related instructions you are required to implement.

#74 conneroisu closed 5 days ago
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assembly report files

#73 conneroisu closed 5 days ago
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assembly report files

#72 conneroisu closed 5 days ago
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assembly report files

#71 conneroisu closed 5 days ago
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remove contract and update workflow

#70 conneroisu closed 5 days ago
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rebase awfoss to aidanfoss

#69 aidanfoss closed 1 day ago
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Project Report

#68 aidanfoss opened 5 days ago
4
44 project report and barrel shifter fix

#67 aidanfoss closed 5 days ago
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#66 github-actions[bot] closed 5 days ago
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#65 github-actions[bot] closed 5 days ago
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8 barrel shifter

#64 aidanfoss closed 6 days ago
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#63 github-actions[bot] closed 6 days ago
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#62 github-actions[bot] closed 6 days ago
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adder subtractor

#61 conneroisu closed 6 days ago
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#60 github-actions[bot] closed 6 days ago
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component/addersub

#59 conneroisu closed 6 days ago
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#58 github-actions[bot] closed 6 days ago
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#57 github-actions[bot] closed 6 days ago
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test/branch

#56 conneroisu closed 6 days ago
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fix header program to get all commits for the file not just the branch

#55 conneroisu closed 6 days ago
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[Part 2 (c.viii)] justify why your test plan is comprehensive. Include waveforms that demonstrate your test programs functioning.

#54 conneroisu closed 6 hours ago
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[Part 4] report the maximum frequency your processor can run at and determine what your critical path is. Draw this critical path on top of your top-level schematics. What components would you focus on to improve the frequency?

#53 conneroisu closed 21 hours ago
1
[Part 3] In your writeup, show the Modelsim output for each of the following tests, and provide a discussion of result correctness. It may be helpful to also annotate the waveforms directly.

#52 conneroisu closed 21 hours ago
3
Synthesize Processor and commit results to the repo

#51 conneroisu closed 21 hours ago
3
[Part 3 (c)] Create and test an application that sorts an array with N elements using the BubbleSort algorithm (link). Name this file Proj1_bubblesort.s.

#50 conneroisu closed 5 days ago
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[Part 3 (a)] Create a test application that makes use of every required arithmetic/logical instruction at least once. The application need not perform any particularly useful task, but it should demonstrate the full functionality of the processor (e.g., sequences of many instructions executed sequentially, 1 per cycle while data written into registers can be effectively retrieved and used by later instructions). Name this file Proj1_base_test.s.

#49 conneroisu closed 5 days ago
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[Part 3 (b)] Create and test an application which uses each of the required control-flow instructions and has a call depth of at least 5 (i.e., the number of activation records on the stack is at least 4). Name this file Proj1_cf_test.s.

#48 conneroisu closed 5 days ago
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[Part 2 (c.iii)] Draw a simplified, high-level schematic for the 32-bit ALU. Consider the following questions: how is Overflow calculated? How is Zero calculated? How is slt implemented?

#47 conneroisu closed 1 day ago
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In your writeup, briefly describe your design approach, including any resources you used to choose or implement the design. Include at least one design decision you had to make.

#46 conneroisu closed 5 days ago
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[Part 2 (c.i.2)] In your writeup, briefly describe how your VHDL code implements both the arithmetic and logical shifting operations.

#45 conneroisu closed 5 days ago
2
[Part 2 (c.i.1)] Describe the difference between logical (srl) and arithmetic (sra) shifts. Why does MIPS not have a sla instruction?

#44 conneroisu closed 5 days ago
1
Draw a schematic for the instruction fetch logic and any other datapath modifications needed for control flow instructions. What additional control signals are needed?

#43 conneroisu closed 5 days ago
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Include your final MIPS processor schematic in your lab report.

#42 conneroisu closed 21 hours ago
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Implement the control logic module using whatever method and coding style you prefer. Create a testbench to test this module individually, and show that your output matches the expected control signals from problem 1(a).

#41 conneroisu closed 1 day ago
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What are the control flow possibilities that your instruction fetch logic must support? Describe these possibilities as a function of the different control flow-related instructions you are required to implement.

#40 conneroisu closed 5 days ago
0
Implement your new instruction fetch logic using VHDL. Use Modelsim to test your design thoroughly to make sure it is working as expected. Describe how the execution of the control flow possibilities corresponds to the Modelsim waveforms in your writeup.

#39 conneroisu closed 21 hours ago
9
[Part 2 (c.i.4)] Describe how the execution of the different shifting operations corresponds to the Modelsim waveforms in your writeup.

#38 conneroisu closed 5 days ago
1
[Part 2 (c.i.3)] In your writeup, explain how the right barrel shifter above can be enhanced to also support left shifting operations.

#37 conneroisu closed 5 days ago
4