[2.b.i] list which instructions produce values, and what signals (i.e., bus names) in the pipeline these correspond to.

[conneroisu]

1. Instructions producing values on the ALU Result signal in the execute stage:

   • add, addi, addiu, addu
   • sub, subu
   • and, andi
   • or, ori
   • xor, xori
   • nor
   • slt, slti
   • sll, srl, sra
   • sllv, srlv, srav

2. Instructions producing/using values on the mem data signal in the memory stage:

   • lw, lh, lhu, lb, lbu (load instructions)
   • sw, sh, sb (store instructions)

3. Instructions producing values on the branchLogic signal going into the fetch logic unit:

   • beq, bne

4. Instructions producing values on the JumpLogic and JregLogic signals going into the fetch logic unit:

   • j, jal
   • jr (uses iJreg signal specifically for register jumping)

[conneroisu]

Instructions consuming values on the s_rs and s_rt signals in the ID stage: Arithmetic and Logical Instructions:

• add, addi, addiu, addu

• sub, subu

• and, andi

• or, ori

• xor, xori

• nor

• slt, slti Shift Instructions:

• sll, srl, sra

• sllv, srlv, srav Memory Access Instructions:

• lw, lh, lhu, lb, lbu, sw Control Flow Instructions:

• jr, bne, beq

Signal Usage:

• Instructions: add, addi, addiu, addu, sub, subu, and, andi, or, ori, xor, xori, nor, sll, srl, sra, sllv, srlv, srav

  • These instructions use signals on the s_rs and s_rt inputs.
  • The immediate (I) variants also utilize the imm signal.

• Instructions: slt, slti, lw, lh, lhu, lb, lbu

  • These instructions consume signals.