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contiki-ng / mspsim

Official MSPSim git repository
BSD 3-Clause "New" or "Revised" License
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allow MSP430 DCO frequency to be up to 9MHz #38

Closed atiselsts closed 9 years ago

atiselsts commented 9 years ago

This is a quick-and-dirty fix for msp430 Series-2 based mote (e.g. Zolertia Z1) clock speed in simulations.

For now, attempts to configure DCO frequency higher than 4.9 MHz in Cooja lead to ACLK speed being reduced to 16384. The outcome is that Contiki system clock on simulated Z1 motes runs twice slower than expected.

Due to some implementation idiosyncrasies, the problem with Z1 clock speed in simulations appeared only after applying this pull request to Contiki: https://github.com/contiki-os/contiki/pull/606 (it fixes a different clock frequency related bug):

Related: issue #35.

simonduq commented 9 years ago

Great! Should also fix https://github.com/mspsim/mspsim/issues/44, right?

atiselsts commented 9 years ago

Hi Simon, yes, you describe the same problem, and this patch is sufficient to get the clock speed back to normal.

issue #35 explains what exactly goes wrong.

simonduq commented 9 years ago

Excellent, thank! On 14 May 2015 10:32, "Atis Elsts" notifications@github.com wrote:

Hi Simon, yes, you describe the same problem, and this patch is sufficient to get the clock speed back to normal.

issue #35 https://github.com/mspsim/mspsim/issues/35 explains what exactly goes wrong.

— Reply to this email directly or view it on GitHub https://github.com/mspsim/mspsim/pull/38#issuecomment-101970805.

joakimeriksson commented 9 years ago

This should now be fixed by #46 so I am closing this.