Translation always uses non-blocking assignments in `tick`

[cbatten]

It looks like we always use a non-blocking assignment to write signals within a tick block even if the user uses the value attribute. The following model works with our pure-Python simulation tool, but fails when we use translation. The generated Verilog is also shown below.

from pymtl import *

class RegIncr2( Model ):

  def __init__( s ):

    s.in_ = InPort  (8)
    s.out = OutPort (8)

    s.temp = Wire(8)

    # Concurrent block

    @s.tick_rtl
    def concurrent_block():
      s.temp.value = s.in_
      s.out.next   = s.temp + 1

  def line_trace( s ):
    return "{} (+1) {}".format( s.in_, s.out )

`default_nettype none
module RegIncr2_0x791afe0d4d8c
(
  input  wire [   7:0] in_,
  input  wire [   0:0] clk,
  input  wire [   0:0] reset,
  output reg  [   7:0] out
);

  // register declarations
  reg    [   7:0] temp;

  // PYMTL SOURCE:
  // @s.tick_rtl
  // def concurrent_block():
  //       s.temp.value = s.in_
  //       s.out.next   = s.temp + 1

  // logic for concurrent_block()
  always @ (posedge clk) begin
    temp <= in_;
    out <= (temp+1);
  end

endmodule // RegIncr2_0x791afe0d4d8c
`default_nettype wire

[dmlockhart]

Duplicate of #78