Translation tool error: zext cannot take an element of WireList

[moyang]

It looks like in a combinational block of a RTL model, zext function does not support taking an element of a WireList. If one does so, that model will fail to translate to Verilog.

For example, suppose one wants to write a 64-bit adder:

...
s.src    = Wire[2](64)
@s.combinational
def comb_logic():
  s.sum.value = zext( s.src[0], 65 ) + zext( s.src[1], 65 )
...

Then the Verilog translation tool will complain: "AttributeError: Problem translating comb_logic() in model Add64UnitRTL_0x791afe0d4d8c: 'WireList' object has no attribute 'nbits'"

It works for a Wire instead of a member of a WireList:

...
s.src0    = Wire(64)
s.src1    = Wire(64)
@s.combinational
def comb_logic():
  s.sum.value = zext( s.src0, 65 ) + zext( s.src1, 65 )
...