Throw useful Error during translation when non-literal Bits constructors encountered.

[dmlockhart]

Bits are only Verilog translatable if the argument provided to them is a numeric literal:

   s.out.value = s.in_ + Bits( 4, 2 )

The following is not supported:

    @s.combinational
    def block():
      s.resp.msg.value = Bits( 32, s.a_reg.out * s.b_reg.out, trunc=True )

It translates to this:

  // PYMTL SOURCE:
  // @s.combinational
  // def block():
  //   s.resp.msg.value = Bits( 32, s.a_reg.out * s.b_reg.out, trunc=True )

  // logic for block()
  always @ (*) begin
    resp_msg = 32'd(a_reg$out*b_reg$out);
  end

The above is invalid Verilog (see 32'd(...)). We should really be able to catch this and throw a useful Exception message to the user.