Type inference from signal lists translate into temporaries with incorrect bitwidth

[dmlockhart]

Given the following code snippet:

  class TestTranslationIssueNNN( Model ):
    def __init__( s ): 
      s.a = InPort [ 2 ]( 4 )
      s.b = OutPort[ 2 ]( 4 )

      @s.combinational
      def logic():
        j = s.a[0]
        s.b[0].value = j
        s.b[1].value = s.a[1]

The bitwidth of temporary j will be inferred as 1 bit instead of 4 bits:

module TestTranslationIssueNNN_0x791afe0d4d8c
(
  input  wire [   3:0] a$000,
  input  wire [   3:0] a$001,
  output wire [   3:0] b$000,
  output wire [   3:0] b$001,
  input  wire [   0:0] clk,
  input  wire [   0:0] reset
);

  // register declarations
  reg    [   0:0] j__0;

  ...

  // logic for logic()
  always @ (*) begin
    j__0 = a[0];
    b[0] = j__0;
    b[1] = a[1];
  end