Import/Translation of two identical Verilog models fails

The CFFI wrapper to Verilator is not object-oriented, so independently translating two identical models (or importing a Verilog component twice to create two instances) fails.

The following Verilog integration test added in commit 30d8b83 provides an example of the problem:

  class EnResetRegParamVRTL( VerilogModel ):
    def __init__( s, p_nbits, p_reset_value=0, p_id=0 ):
      s.en  = InPort ( 1 )
      s.d   = InPort ( p_nbits )
      s.q   = OutPort( p_nbits )

  class ModelChainer( Model ):
    def __init__( s, nbits, rst=0 ):
      s.en  = InPort ( 1 )
      s.d   = InPort ( nbits )
      s.q   = OutPort( nbits )

      s.mod = m = [EnResetRegParamVRTL( nbits, rst, x ) for x in range(3)]

      for x in s.mod:
        s.connect( s.en, x.en )

      s.connect_dict({
        s.d    : m[0].d,
        m[0].q : m[1].d,
        m[1].q : m[2].d,
        m[2].q : s.q,
      })

cornell-brg / pymtl

Import/Translation of two identical Verilog models fails #139