Verilog Translation Bug: Accessing fields from array of PortBundles not working

[stevedai]

For a model as shown below, if we try to access a field from a specific PortBundle given an array of PortBundles,

from pymtl import *

from pclib.ifcs import InValRdyBundle, OutValRdyBundle, valrdy_to_str
from pclib.ifcs.MemMsg import *

class foo( Model ):
  def __init__( s ):

    #---------------------------------------------------------------------
    # Interface
    #---------------------------------------------------------------------

    s.in_ = [ InValRdyBundle( MemReqMsg( 32, 32 ) ) for i in xrange(2)]

    s.out = OutPort( 32 )

    @s.combinational
    def foo():
      s.out.value = s.in_[0].msg.data

PyMTL translation breaks and throws the error below:

Traceback (most recent call last):
  File "generate_verilog.py", line 4, in <module>
    model = TranslationTool( model )
  File "/work/zhang/common/tools/pymtl/pymtl/pymtl/tools/translation/verilator_sim.py", line 44, in TranslationTool
    verilog.translate( model_inst, fd )
  File "/work/zhang/common/tools/pymtl/pymtl/pymtl/tools/translation/verilog.py", line 46, in translate
    translate_module( v, o )
  File "/work/zhang/common/tools/pymtl/pymtl/pymtl/tools/translation/verilog.py", line 57, in translate_module
    logic, symtab = translate_logic_blocks( model )
  File "/work/zhang/common/tools/pymtl/pymtl/pymtl/tools/translation/verilog_behavioral.py", line 46, in translate_logic_blocks
    new_tree   = ast_pipeline( tree, model, func )
  File "/work/zhang/common/tools/pymtl/pymtl/pymtl/tools/translation/verilog_behavioral.py", line 131, in ast_pipeline
    tree = visitors.PortListNameHack   ( model       ).visit( tree )
  File "/work/zhang/common/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/work/zhang/common/usr/lib/python2.7/ast.py", line 297, in generic_visit
    value = self.visit(value)
  File "/work/zhang/common/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/work/zhang/common/usr/lib/python2.7/ast.py", line 306, in generic_visit
    new_node = self.visit(old_value)
  File "/work/zhang/common/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/work/zhang/common/usr/lib/python2.7/ast.py", line 306, in generic_visit
    new_node = self.visit(old_value)
  File "/work/zhang/common/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/work/zhang/common/usr/lib/python2.7/ast.py", line 306, in generic_visit
    new_node = self.visit(old_value)
  File "/work/zhang/common/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/work/zhang/common/tools/pymtl/pymtl/pymtl/tools/translation/visitors.py", line 742, in visit_Subscript
    if plist.parent != self.model and not '$' in plist.name:
  File "/work/zhang/common/tools/pymtl/pymtl/pymtl/model/signal_lists.py", line 27, in parent
    return self[0].parent
AttributeError:
Unexpected error during VerilogTranslation!
Please contact the PyMTL devs!
'_LeftValRdyBundle' object has no attribute 'parent'

> <unknown>

File:      /work/zhang/users/dai/fpga-2016/pymtl_examples/hls_misc/foo.py
Model:     foo_0x791afe0d4d8c
Function:  foo
Line:      ~20

[Crafted with Shreesha]