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cornell-brg / pymtl

Python-based hardware modeling framework
BSD 3-Clause "New" or "Revised" License
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Verilator xinit #149

Closed taylorpritchard closed 8 years ago

cbatten commented 8 years ago

I already talked to Taylor about commit message conventions for future commits. I will take a quick look and merge this in tonight and also email BRG to let them know about this change.

@taylorpritchard Did you try a specific register file test that fails with --test-verilog='ones'? Or do we need to add that?

taylorpritchard commented 8 years ago

@cbatten There is one test that fails with --test-verilog='ones' (provided the code is added to the test file to pass through the argument to the translation tool)

cbatten commented 8 years ago

OK. This looks great. It looks like the current tests in RegisterFile_test.py actually incorrectly assumed the register state was initialized to zero. So I fixed that in the test cases, then I added a new test case named test_regfile_1R1Wconst0 which passes even though we do not explicitly check on a read to ensure that we always return 0 when reading r0. So this passes:

 % py.test ./RegisterFile_test.py -k const0
 % py.test ./RegisterFile_test.py -k const0 --test-verilog

However, with the new features that @taylorpritchard added, we can force Verilator to set all uninitialized state to ones and then it fails:

 % py.test ./RegisterFile_test.py -k const0 --test-verilog='ones'

So I am going to go ahead and merge this into the ece4750 branch and then master. Thanks @taylorpritchard!

cbatten commented 8 years ago

We already merged this into the master branch