Allow empty functions to be elaborated during translation

cornell-brg / pymtl

Python-based hardware modeling framework

BSD 3-Clause "New" or "Revised" License

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Allow empty functions to be elaborated during translation #165

Open kkiningh opened 7 years ago

kkiningh commented 7 years ago

Previously, the following code would error during translation:

class Alu(Model):
        def elaborate_logic(self):
            @self.combinational
            def comb(): 
                pass

This pull request fixes that.

cbatten commented 7 years ago

Interesting! Can you maybe explain where this programming pattern is common?

kkiningh commented 7 years ago

I removed the body of a combinational block to debug something. I don't know if that's common, but it doesn't seem like something the compiler should give a cryptic "Unexpected error during VerilogTranslation!" on.