when use, there is an error list index out of range in metaclasses.py in the floder named model

[tristantian]

when I run the the project ,there is an error shown as File "metaclasses.py" line 91, in call key, value = argspec.args[i+1], arg_value IndexError: list index out of range And I use "py.test .." to test the pymtl, there are 183 failed. How should I do?

[cbatten]

Can you provide step-by-step instructions to reproduce the issue along with details on your environment (i.e., OS, Python version, py.test version, etc). Here are the expected test results:

• https://travis-ci.org/cornell-brg/pymtl/jobs/479591423

993 passed, 8 skipped, 52 xfailed, 8 xpassed. There should be no failures if everything is installed correctly and working.

[tristantian]

Can you provide step-by-step instructions to reproduce the issue along with details on your environment (i.e., OS, Python version, py.test version, etc). Here are the expected test results:

* https://travis-ci.org/cornell-brg/pymtl/jobs/479591423

993 passed, 8 skipped, 52 xfailed, 8 xpassed. There should be no failures if everything is installed correctly and working.

I run the test using ubuntu 18.04. The environment is configured by readme.

Here are the informations about environment and test results,when use command "py.test ..": Python 2.7.15rc1 pip 9.0.1 from /usr/lib/python2.7/dist-packages (python 2.7) Verilator 3.876 2015-08-12 rev verilator_3_876-1-g5f21385

platform linux2 -- Python 2.7.15rc1, pytest-4.1.1, py-1.7.0, pluggy-0.8.1 rootdir: /home/tristan/pymtl/cornell/pymtl, inifile: pytest.ini plugins: xdist-1.26.0, forked-1.0.1 collected 1061 items
../pclib/cl/InValRdyRandStallAdapter_test.py ......... [ 0%] ../pclib/cl/OutValRdyInelasticPipeAdapter_test.py ................... [ 2%] ../pclib/cl/adapters_test.py ..... [ 3%] ../pclib/cl/pipelines_test.py ................................... [ 6%] ../pclib/cl/queues_test.py ............................................. [ 10%] ...................... [ 12%] ../pclib/fl/BytesMemPortAdapter_test.py .... [ 13%] ../pclib/fl/Bytes_test.py ... [ 13%] ../pclib/fl/ListBytesProxy_test.py . [ 13%] ../pclib/fl/QueuePortProxy_test.py .... [ 13%] ../pclib/ifcs/MemMsg_test.py .... [ 14%] ../pclib/ifcs/NetMsg_test.py .. [ 14%] ../pclib/ifcs/ValRdyBundle_test.py ..... [ 14%] ../pclib/ifcs/XcelMsg_test.py .... [ 15%] ../pclib/rtl/Bus_test.py . [ 15%] ../pclib/rtl/Crossbar_test.py . [ 15%] ../pclib/rtl/Decoder_test.py .. [ 15%] ../pclib/rtl/Mux_test.py ....... [ 16%] ../pclib/rtl/PipeCtrl_test.py ......... [ 17%] ../pclib/rtl/RegisterFile_test.py ... [ 17%] ../pclib/rtl/SRAMs_test.py .... [ 17%] ../pclib/rtl/arbiters_test.py .. [ 18%] ../pclib/rtl/arith_test.py ..................... [ 19%] ../pclib/rtl/onehot_test.py .. [ 20%] ../pclib/rtl/queues_test.py .................. [ 21%] ../pclib/rtl/regs_test.py ........ [ 22%] ../pclib/test/SparseMemoryImage_test.py s [ 22%] ../pclib/test/TestMemory_test.py ....................... [ 24%] ../pclib/test/TestNetSink_test.py ........ [ 25%] ../pclib/test/TestRandomDelay_test.py .... [ 26%] ../pclib/test/TestSimpleNetSink_test.py ... [ 26%] ../pclib/test/TestSimpleSink_test.py . [ 26%] ../pclib/test/TestSink_test.py ............ [ 27%] ../pclib/test/TestSource_test.py ........ [ 28%] ../pclib/test/TestSrcSinkSim_test.py .... [ 28%] ../pclib/test/TestSynchronizer_test.py ....... [ 29%] ../pclib/test/TestVectorSimulator_test.py . [ 29%] ../pymtl/datatypes/BitStruct_test.py .x....x [ 30%] ../pymtl/datatypes/Bits_test.py ................................... [ 33%] ../pymtl/datatypes/helpers_test.py ........ [ 34%] ../pymtl/model/Model_test.py ............. [ 35%] ../pymtl/model/PortBundle_test.py ..... [ 35%] ../pymtl/tools/deprecated/ast_transformer_test.py ...................... [ 37%] ....... [ 38%] ../pymtl/tools/deprecated/ast_typer_test.py ............................ [ 41%] . [ 41%] ../pymtl/tools/integration/verilog_tests/verilog_test.py FFFFFFFFFFFFFFF [ 42%] FFFFFFFFFFFFF.. [ 44%] ../pymtl/tools/simulation/SimulationTool_bug_test.py ............... [ 45%] ../pymtl/tools/simulation/SimulationTool_comb_test.py .................. [ 47%] .......................................... [ 51%] ../pymtl/tools/simulation/SimulationTool_mix_test.py ............ [ 52%] ../pymtl/tools/simulation/SimulationTool_seq_test.py .............. [ 53%] ../pymtl/tools/simulation/SimulationTool_struct_test.py ................ [ 55%] ................... [ 56%] ../pymtl/tools/simulation/SimulationTool_transl_test.py ........x...x.x. [ 58%] .....X..x.................................................. [ 63%] ../pymtl/tools/simulation/SimulationTool_wire_test.py ...........X [ 65%] ../pymtl/tools/simulation/ast_visitor_test.py .......................... [ 67%] ................. [ 69%] ../pymtl/tools/simulation/vcd_test.py .................................. [ 72%] ........................................................................ [ 79%] .......X [ 79%] ../pymtl/tools/translation/verilator_sim_test.py FF [ 80%] ../pymtl/tools/translation/verilog_behavioral_test.py sssFFFFFFFFFFFFFFF [ 81%] FFFFFFFFFFFFxFFFFFFFFFFFFFFFFFFxsFFFFxFFFFFFFFFFFFFFFsssFFFFFFFFFFFxxFFF [ 88%] xFFxxxxFxxFFxxxxxxFxxxxxxxxxxxxxxxxxxxFFFFFFFFxxxxxxxxxFFFFFFFFFFFF [ 94%] ../pymtl/tools/translation/verilog_bug_test.py FFFF. [ 95%] ../pymtl/tools/translation/verilog_structural_test.py FFFFFFFFFFFFFFFFFF [ 97%] FFFFFFFFFFFFFFFxxFFFFFFFFFFFxFx [100%]

== 183 failed, 811 passed, 8 skipped, 56 xfailed, 3 xpassed in 46.78 seconds ===

[cbatten]

Hmm ... the verilog tests seem to be failing. Can you post what the exact error is you are seeing? So try this:

 % py.test ../pymtl/tools/integration/verilog_tests/verilog_test.py -x --tb=long

Can you verify that you have installed Verilator correctly? Does this work:

 % pkg-config --print-variables verilator

Or are you using the PYMTL_VERILATOR_INCLUDE_DIR environment variable?

[tristantian]

I'm new to pymtl. Thank you for helping me. % pkg-config --print-variables verilator datarootdir exec_prefix includedir libdir pcfiledir prefix

And here are teh output after using the command you provided: ../pymtl/tools/integration/verilog_tests/verilog_test.py F

=================================== FAILURES =================================== ___ test_Reg[4-True] ___

dump_vcd = '', nbits = 4, all_verilog = True

@pytest.mark.parametrize( "nbits,all_verilog",
 [(4,True),(128,False)]
)
def test_Reg( dump_vcd, nbits, all_verilog ):

  class vc_Reg( VerilogModel ):
    vcd_file   = dump_vcd  # TODO: hack for issue #135
    modulename = 'vc_Reg'
    sourcefile = os.path.join( os.path.dirname(__file__),
                               'vc-regs.v' )

    def __init__( s, nbits ):
      s.in_ = InPort ( nbits )
      s.out = OutPort( nbits )

      s.set_params({
        'p_nbits' : nbits,
      })

      s.set_ports({
        'clk' : s.clk,
        'd'   : s.in_,
        'q'   : s.out,
      })

  #---------------------------------------------------------------------
  # test
  #---------------------------------------------------------------------

m, sim = _sim_setup( vc_Reg(nbits), all_verilog, dump_vcd )

../pymtl/tools/integration/verilog_tests/verilog_test.py:51:

---

self = <class 'verilog_test.vc_Reg'>, args = (4,), kwargs = {} inst = <verilog_test.vc_Reg object at 0x7f1ca569d650> TranslationTool = <function TranslationTool at 0x7f1ca56f5500>

def __call__( self, *args, **kwargs ):
  inst = super( SomeMeta, self ).__call__( *args, **kwargs )

  # TODO: THIS IS SUPER HACKY. FIXME
  # We import TranslationTool here because of circular imports...
  from ..translation.verilator_sim import TranslationTool

  # TODO: THIS IS SUPER HACKY. FIXME
  # After the VerilogModel has been constructed and __init__ has
  # completed, pass the VerilogModel into the TranslationTool.
  # We need to do this **before** elaboration, and before the parent who
  # instantiated us completes their initialization. This is because if
  # we wait, then we'll have to find all the references to the
  # original VerilogModel and its ports/other members and swap them!
  #
  # A simpler but less user friendly way to do this is to force the user
  # to **always** wrap instantiations of VerilogModels in the
  # TranslationTool explicitly, like so:
  #
  # >>> my_verilog_model = TranslationTool( MyVerilogModel( p1, p2 ) )
  #

  # I think there is no way to turn on VCD dumping after the fact, so I
  # think we have no choice but to always turn on VCD dumping for now
  # if we are using Verilog import? -cbatten

  inst.vcd_file = '__dummy__'

new_inst = TranslationTool( inst, lint=True )

../pymtl/tools/integration/verilog.py:58:

---

model_inst = <verilog_test.vc_Reg object at 0x7f1ca569d650>, lint = True enable_blackbox = False, verilator_xinit = 'zeros'

def TranslationTool( model_inst, lint=False, enable_blackbox=False, verilator_xinit="zeros" ):
  """Translates a PyMTL model into Python-wrapped Verilog.

  model_inst:      an un-elaborated Model instance
  lint:            run verilator linter, warnings are fatal
                   (disables -Wno-lint flag)
  enable_blackbox: also generate a .v file with black boxes
  """

  model_inst.elaborate()

  # Translate the PyMTL module to Verilog, if we've already done
  # translation check if there's been any changes to the source
  model_name      = model_inst.class_name
  verilog_file    = model_name + '.v'
  temp_file       = model_name + '.v.tmp'
  c_wrapper_file  = model_name + '_v.cpp'
  py_wrapper_file = model_name + '_v.py'
  lib_file        = 'lib{}_v.so'.format( model_name )
  obj_dir         = 'obj_dir_' + model_name
  blackbox_file   = model_name + '_blackbox' + '.v'

  vcd_en   = True
  vcd_file = ''
  try:
    vcd_en   = ( model_inst.vcd_file != '' )
    vcd_file = model_inst.vcd_file
  except AttributeError:
    vcd_en = False

  # Write the output to a temporary file
  with open( temp_file, 'w+' ) as fd:
    verilog.translate( model_inst, fd, verilator_xinit=verilator_xinit )

  # write Verilog with black boxes
  if enable_blackbox:
    with open( blackbox_file, 'w+' ) as fd:
      verilog.translate( model_inst, fd, enable_blackbox=True, verilator_xinit=verilator_xinit )

  # Check if the temporary file matches an existing file (caching)

  cached = False
  if (     exists(verilog_file)
       and exists(py_wrapper_file)
       and exists(lib_file)
       and exists(obj_dir) ):

    cached = filecmp.cmp( temp_file, verilog_file )

    # if not cached:
    #   os.system( ' diff %s %s'%( temp_file, verilog_file ))

  # Rename temp to actual output
  os.rename( temp_file, verilog_file )

  # Verilate the module only if we've updated the verilog source
  if not cached:
    #print( "NOT CACHED", verilog_file )
    verilog_to_pymtl( model_inst, verilog_file, c_wrapper_file,
                      lib_file, py_wrapper_file, vcd_en, lint,

                    verilator_xinit )

../pymtl/tools/translation/verilator_sim.py:78:

---

model = <verilog_test.vc_Reg object at 0x7f1ca569d650> verilog_file = 'vc_Reg_0x13b09ee6e23ad41b.v' c_wrapper_file = 'vc_Reg_0x13b09ee6e23ad41b_v.cpp' lib_file = 'libvc_Reg_0x13b09ee6e23ad41b_v.so' py_wrapper_file = 'vc_Reg_0x13b09ee6e23ad41b_v.py', vcd_en = True, lint = True verilator_xinit = 'zeros'

def verilog_to_pymtl( model, verilog_file, c_wrapper_file,
                      lib_file, py_wrapper_file, vcd_en, lint, verilator_xinit ):

  model_name = model.class_name

  try:
    vlinetrace = model.vlinetrace
  except AttributeError:
    vlinetrace = False

  # Verilate the model  # TODO: clean this up

verilate_model( verilog_file, model_name, vcd_en, lint )

../pymtl/tools/translation/verilator_cffi.py:34:

---

filename = 'vc_Reg_0x13b09ee6e23ad41b.v' model_name = 'vc_Reg_0x13b09ee6e23ad41b', vcd_en = True, lint = True

def verilate_model( filename, model_name, vcd_en, lint ):

  # verilator commandline template

  compile_cmd = ( 'verilator -cc {source} -top-module {model_name} '
                  '--Mdir {obj_dir} -O3 {flags}' )

  # verilator commandline options

  source  = filename
  obj_dir = 'obj_dir_' + model_name
  flags   = ' '.join([
              '-Wno-lint' if not lint else '',
              '-Wno-UNOPTFLAT',
              '--unroll-count 1000000',
              '--unroll-stmts 1000000',
              '--assert',
              '--trace' if vcd_en else '',
            ])

  # remove the obj_dir because issues with staleness

  if os.path.exists( obj_dir ):
    shutil.rmtree( obj_dir )

  # create the verilator compile command

  compile_cmd = compile_cmd.format( **vars() )

  # try compilation

  try:
    # print( compile_cmd )
    result = check_output( compile_cmd, stderr=STDOUT, shell=True )
    # print( result )

  # handle verilator failure

  except CalledProcessError as e:
    # error_msg = """
    #   Module did not Verilate!
    #
    #   Command:
    #   {command}
    #
    #   Error:
    #   {error}
    # """

    # We remove the final "Error: Command Failed" line to make the output
    # more succinct.

    split_output = e.output.splitlines()
    error = '\n'.join(split_output[:-1])

    if not split_output[-1].startswith("%Error: Command Failed"):
      error += "\n"+split_output[-1]

    error_msg = """
See "Errors and Warnings" section in the manual located here
http://www.veripool.org/projects/verilator/wiki/Manual-verilator
for more details on various Verilator warnings and error messages.

{error}"""

    raise VerilatorCompileError( error_msg.format(
      command = e.cmd,

    error   = error

)) E VerilatorCompileError: E See "Errors and Warnings" section in the manual located here E http://www.veripool.org/projects/verilator/wiki/Manual-verilator E for more details on various Verilator warnings and error messages. E
E %Error: Verilator internal fault, sorry. Consider trying --debug --gdbbt

../pymtl/tools/translation/verilator_cffi.py:125: VerilatorCompileError =========================== 1 failed in 0.22 seconds ===========================

[cbatten]

Yeow. Verilator internal error. Not sure what to do about that? Do you get the same error for all the failing tests? Did you get any errors when compiling verilator from source?

Do you need the verilog import features of PyMTL? If not the you can still use PyMTL as is.

[cbatten]

I wonder if it has something to do with compiling the older version of verilator on Ubuntu 18.04. Can you try installing the most recent version of verilator?

[tristantian]

Thank you ，I update version of the verilator to 3.916，and it can work now.

[cbatten]

Great! We were stuck on using 3.876 for a while because of some bug, but maybe that was fixed and we can now upgrade to using the most recent version of Verilator. Let us know if you see any issues with the most recent version of Verilator ...