List of Wires in Concurrent Block translate incorrectly

[dmlockhart]

List of Wires read-only in a concurrent block don't translate properly (generated as regs instead of wires and assigned to signals improperly):

class ListOfWires( Model ):
  def __init__( s ):
    s.in_ = [ InPort ( 4 ) for x in range(2) ]
    s.out = [ OutPort( 4 ) for x in range(2) ]

  def elaborate_logic( s ):
    s.wire_rd = [ Wire( 4 ) for x in range(2) ]
    s.wire_wr = [ Wire( 4 ) for x in range(2) ]

    for i in range(2):
      s.connect( s.in_[i], s.wire_rd[i] )
      s.connect( s.out[i], s.wire_wr[i] )

    @s.combinational
    def logic():
      for i in range(2):
        s.wire_wr[i].value = s.wire_rd[i]