SubModule PortBundles accessed in a behavioral block translate incorrectly

[dmlockhart]

The following source:

    @s.combinational
    def logic():
      for i in range(2):
        s.submod.bundle.port.value = s.signal

Will translate the "s.submodule.bundle.port" to simply "port" in verilog, although it should be translated to "submodule_bundle_port".