Accessing PortBundles of Submodule List in Concurrent Block translates incorrectly

[dmlockhart]

Accessing the portbundle of a submodule list inside a concurrent block does not translate names correctly:

 def elaborate_logic( s ): 
    s.submod = [BundleChild( 4 ) for x in range(2)]
    @s.combinational
    def logic1():
      for i in range(2):
        s.submod[i].in_.a.value = s.in_[i].a
        s.out[i].b.value = s.submod[i].out.b