Accessing Submodule PortList in Concurrent Block translates incorrectly

[dmlockhart]

Temporary array generation creates incorrect array names for the following code:

class SubmodPortList( Model ):
  def __init__( s ): 
    s.in_ = InPort [2]( 4 )
    s.out = OutPort[2]( 4 )
    s.submod = ListOfWires()
    @s.combinational
    def logic_in():
      s.submod.in_[0].value = s.in_[0]
      s.submod.in_[1].value = s.in_[1]
  ...