Member and temporary variables with same name cause problems in verilog translation

[dmlockhart]

The following code in PyMTL is valid, but causes issues during Verilog translation:

  def __init__(s):
    s.in_ = InPort(1)
    s.signal_name = OutPort(1)
  def elaborate_logic(s):
    s.combinational
    def logic():
      signal_name = s.another_signal

This will result in a redundant (and erroneous) signal declaration in the translated Verilog:

  ...
  input wire [0:0] in_,
  output wire [0:0] signal_name
  ...
  reg [0:0] signal_name;