Phase Locked Loop (PLL)

[jjm469]

A PLL serves as a versatile hardware module that can generate stable clock signals with specific frequencies and phases. PLLs, enable digital designers to generate multiple clock domains and adjust clock frequencies as needed for various components of their design.

We need 1 - 2 people to work on creating this block for our IP catalog.

Potentially Helpful readings: https://zipcpu.com/dsp/2017/12/14/logic-pll.html https://en.wikipedia.org/wiki/Phase-locked_loop

[gabizon103]

Not sure what we want to use this for specifically, but would it be possible to do this with some clock dividers? We might not need to set specific frequencies or phases, and if we just want to generate a slower clock signal then clock dividers should do the job

[jjm469]

Forgive any gaps in my knowledge, but here is how I understand it. We can use a PLL to generate a clock signal, which I am assuming we need. Unless, one of the tools we uses already does this for us, in which case maybe clock dividers would be the more useful project.

[tomaschoi03]

Sources using: https://zipcpu.com/dsp/2017/12/14/logic-pll.html https://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf https://bjpcjp.github.io/pdfs/cmos_layout_sim/ch19-digital-plls.pdf https://web.engr.oregonstate.edu/~moon/research/files/cas2_mar_07_dpll.pdf